Method for removing threshold voltage adjusting layer with external acid diffusion process

• US 8,227,307 B2
• Filed: 06/24/2009
• Issued: 07/24/2012
• Est. Priority Date: 06/24/2009
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Kuang-Jung, Donaton, Ricardo A., Huang, Wu-Song, Li, Wai-Kin
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US12/490,353
• Publication Number:
  US 20100330810A1
• Time in Patent Office: 1,126 Days
• Field of Search: 438/703, 438/199, 430/275.1
• US Class Current: 438/199
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

Claims

1. A method of forming a semiconductor structure comprising:

forming a threshold voltage adjusting layer atop a high k gate dielectric that is located above a semiconductor substrate;

forming a patterned mask protecting a portion of the threshold voltage adjusting layer, while leaving another portion of the threshold voltage adjusting layer unprotected;

forming an acid polymer atop the patterned mask and atop an exposed portion of the threshold voltage adjusting layer, said acid polymer comprises a polymerized compound or mixture of compounds comprising repeating structural units including at least one acid functional group attached thereto;

baking the acid polymer to increase the acid concentration in the acid polymer and to diffuse acid moieties into the exposed portion of the threshold voltage adjusting layer which react with the exposed threshold voltage adjusting layer to provide an acid reacted threshold voltage adjusting layer;

removing the baked acid polymer using an aqueous solution or an organic solvent;

removing the patterned mask and the acid reacted threshold voltage adjusting layer, wherein at least said acid reacted threshold voltage layer is removed by a dry etching process selected from the group consisting of reactive ion etching, ion beam etching, plasma etching and laser ablation; and

forming a conductive material atop remaining portions of the threshold voltage adjusting layer.

2. The method of claim 1 wherein said threshold voltage adjusting layer is a pFET threshold voltage adjusting material or an nFET threshold voltage adjusting material.

3. The method of claim 2 wherein said threshold voltage adjusting layer is an nFET threshold voltage adjusting material selected from an oxide or nitride of at least one element from Group IIIB of the Periodic Table of Elements or an alkaline earth metal-containing material having a formula MA_X wherein M is an alkaline earth metal and A is one of O, S and a halide and x is 1 or 2.

4. The method of claim 3 wherein said nFET threshold voltage adjusting material is an oxide from Group IIIB of the Periodic Table of Elements.

5. The method of claim 2 wherein said threshold voltage adjusting layer is a pFET threshold voltage adjusting material selected from an oxide of aluminum, germanium, titanium or tantalum.

6. The method of claim 1 wherein said forming the acid polymer includes selecting a polymer comprising a sulfur-containing acidic moiety.

7. The method of claim 6 wherein said sulfur-containing acidic moiety is a sulfonic acid moiety.

8. The method of claim 7 wherein said sulfonic acid moiety is a fluorosulfonic acid.

9. The method of claim 1 wherein said forming the acid polymer includes selecting a salt of a strong acid.

10. The method of claim 9 wherein said salt of the strong acid is an ammonium salt.

11. The method of claim 1 wherein said acid polymer after baking has a pH value that is greater than about 2.

12. A method of forming a semiconductor structure comprising:

forming a first threshold voltage adjusting layer atop a high k gate dielectric that is located above a semiconductor substrate having a first device region and a second device region;

forming a first patterned mask protecting a portion of the threshold voltage adjusting layer within the first device region, while leaving another portion of the first threshold voltage adjusting layer within the second device region unprotected;

forming a first acid polymer atop the first patterned mask and atop an exposed portion of the threshold voltage adjusting layer, said first acid polymer comprises a polymerized compound or mixture of compounds comprising repeating structural units including at least one acid functional group attached thereto;

baking the first acid polymer to increase the acid concentration in the first acid polymer and to diffuse acid moieties into the exposed portion of the first threshold voltage adjusting layer which react with the first exposed threshold voltage adjusting layer to provide an acid reacted first threshold voltage adjusting layer within the second device region that laterally abuts a non-acid reacted first threshold voltage adjusting layer within the first device region;

removing the baked first acid polymer using an aqueous solution or an organic solvent;

removing the first patterned mask and the first acid reacted threshold voltage adjusting layer, wherein at least said first acid reacted threshold voltage adjusting layer is removed by a dry etching process selected from the group consisting of reactive ion etching, ion beam etching, plasma etching and laser ablation;

forming a second threshold voltage adjusting layer atop the high k gate dielectric and the non-acid reacted first threshold voltage adjusting layer;

forming a second patterned mask protecting a portion of the second threshold voltage adjusting layer within the second device region, while leaving another portion of the second threshold voltage adjusting layer within the first device region unprotected;

forming a second acid polymer atop the second patterned mask and atop the exposed portion of the second threshold voltage adjusting layer, said second acid polymer comprises another polymerized compound or mixture of compounds comprising repeating structural units including at least one acid functional group attached thereto;

baking the second acid polymer to increase the acid concentration in the second acid polymer and to diffuse acid moieties into the exposed portion of the second threshold voltage adjusting layer which react with the exposed second threshold voltage adjusting layer to provide a second acid reacted threshold voltage adjusting layer in the first device region abutting a non-acid reacted second threshold voltage adjusting layer in the second device region;

removing the second baked acid polymer using an aqueous solution or an organic solvent;

removing the second patterned mask and the second acid reacted threshold voltage adjusting layer from the first device region, wherein at least said second acid reacted threshold voltage adjusting layer is removed by a dry etching process selected from the group consisting of reactive ion etching, ion beam etching, plasma etching and laser ablation; and

forming a conductive material atop remaining portions of the first threshold voltage adjusting layer and the second threshold voltage adjusting layer.

13. The method of claim 12 wherein said first threshold voltage adjusting layer is a pFET threshold voltage adjusting material or an nFET threshold voltage adjusting material, and the second threshold voltage adjusting layer is the other of the pFET threshold voltage adjusting material or the nFET threshold voltage adjusting material not employed as the first threshold voltage adjusting layer.

14. The method of claim 13 wherein the nFET threshold voltage adjusting material is selected from an oxide or nitride of at least one element from Group IIIB of the Periodic Table of Elements or an alkaline earth metal-containing material having a formula MA_X wherein M is an alkaline earth metal and A is one of O, S and a halide and x is 1 or 2.

15. The method of claim 13 wherein said pFET threshold voltage adjusting material is selected from an oxide of aluminum, germanium, titanium or tantalum.

16. The method of claim 12 wherein said first and second acid polymers include a polymer comprising a sulfur-containing acidic moiety.

17. The method of claim 16 wherein said sulfur-containing acidic moiety is a sulfonic acid moiety.

18. The method of claim 17 wherein said sulfonic acid moiety is a fluorosulfonic acid.

19. The method of claim 12 wherein said first and second acid polymers include a salt of a strong acid.

20. The method of claim 19 wherein said salt of the strong acid is an ammonium salt.