Multilayer ceramic substrate, electronic component, and method of manufacturing multilayer ceramic substrate

• US 8,227,702 B2
• Filed: 03/31/2009
• Issued: 07/24/2012
• Est. Priority Date: 04/02/2008
• Status: Active Grant

• Current Assignee: Proterial Ltd.
• Original Assignee: Hitachi Metals (Thailand) Ltd.
• Inventors: Ichikawa, Koji, Ikeda, Hatsuo
• Primary Examiner(s): VU, HIEN D
• Application Number:
  US12/385,134
• Publication Number:
  US 20090251869A1
• Time in Patent Office: 1,211 Days
• Field of Search: 174/256, 174/261, 174/262, 174/266, 361/760
• US Class Current: 174/256
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/09745 Recess in conductor, e.g. in pad or in metallic substrate
• CPC Class Codes: H05K 3/246 Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
• CPC Class Codes: H05K 3/4061 for via connections in inorganic insulating substrates
• CPC Class Codes: H05K 3/4611 by laminating two or more circuit boards H05K3/4652 takes precedence
• CPC Class Codes: H05K 3/4629 laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Abstract

A multilayer ceramic substrate in which an active element and a passive element are surface-equipped over the outermost surface on one side is provided. The multilayer ceramic substrate comprises a plurality of laminated ceramic substrate layers, a surface layer terminal electrode provided in a via hole of an outermost ceramic substrate layer on at least one side and having a surface layer via electrode and a metal plating layer deposited over an end surface of the surface layer via electrode, and a via conductor which connects the surface layer terminal electrode and circuit patterns over the ceramic substrate layer at the inside, wherein a via hole size of a surface layer terminal electrode for connection of the active element is smaller than a via hole size of a surface layer terminal electrode for connection of the passive element.

Claims

1. A multilayer ceramic substrate in which a plurality of ceramic substrate layers are laminated, the multilayer ceramic substrate comprising:

a surface layer terminal electrode which is provided at an outermost ceramic substrate layer on at least one side of a front side and a back side and which comprises a surface layer via electrode and a metal plating layer deposited over an end surface of the surface layer via electrode; and

a via conductor which connects the surface layer terminal electrode and circuit patterns over an internal ceramic substrate layer,

wherein the surface layer via electrode has it-s-the end surface in a via hole provided in the outermost ceramic substrate layer and at a level recessed from a surface of the outermost ceramic substrate layer, and a surface of the metal plating layer deposited over the end surface of the surface layer via electrode is at substantially same plane level as the surface of the outermost ceramic substrate layer or at a level recessed from the surface of the outermost ceramic substrate layer,

wherein the metal plating layer matches, without a gap, at a boundary contacting an inner wall of the via hole.

2. The multilayer ceramic substrate according to claim 1, wherein

a ratio (d/φ

) between a depth (d;

with a direction toward inside of the substrate being negative) of the end surface of the surface layer via electrode when the surface of the outermost ceramic substrate layer is a ±

0 reference plane and a diameter (φ

) of the via hole is a negative value between 0 and −

0.12.

3. The multilayer ceramic substrate according to claim 1, wherein

the metal plating layer matches, without a gap, at a boundary contacting an inner wall of the via hole, and

when the boundary is viewed in a cross section along a depth direction, a contact length (L) of the boundary is greater than or equal to 2 μ

m.

4. The multilayer ceramic substrate according to claim 1, wherein

the metal plating layer matches, without a gap, at a boundary contacting inner walls of the via holes, and

when the boundary is viewed in a cross section along a depth direction, the boundary has a roughness width (w) of a maximum and minimum of projections and recesses of greater than or equal to 0.6 μ

m.

5. The multilayer ceramic substrate according to claim 1, wherein

the metal plating layer comprises a Ni base layer and a Au coverage layer, and

a thickness of the Ni base layer deposited over the end surface of the surface layer via electrode is greater than or equal to 3 μ

m.

6. The multilayer ceramic substrate according to claim 1, wherein

the via hole provided in the outermost ceramic substrate layer is formed in a tapered hole shape which widens toward the outermost surface.

7. The multilayer ceramic substrate according to claim 1, wherein

an active element and a passive element are to be mounted on a surface of the multilayer ceramic substrate, and

a via hole size of a surface layer terminal electrode for connection of the active element is smaller than a via hole size of a surface layer terminal electrode for connection of the passive element.

8. The multilayer ceramic substrate according to claim 7, wherein

for via holes for active element and passive element of the outermost ceramic substrate layer on one side, a conductor paste is filled to form a surface layer via electrode, and, for at least the via hole for the passive element, a surface layer pad electrode having a double conductor structure is formed using a conductor paste having a relatively small volume shrinkage ratio during sintering compared to the conductor paste filled to form a surface layer via electrode.

9. An electronic component which uses the multilayer ceramic substrate according to claim 1, wherein a surface mounting component is mounted using a solder ball over the metal plating layer.

10. The electronic component according to claim 9, wherein

a surface layer terminal electrode for connection of the active element of the multilayer ceramic substrate is connected using a solder ball (bump) over a metal plating layer in the via hole, and a surface terminal electrode for connection of the passive element is connected using a solder paste over the surface of the metal plating layer deposited over the surface layer pad electrode outside of the via hole.

11. The electronic component according to claim 10, wherein

a height of the surface of the metal plating layer for connection of the passive element is higher than a height of the surface of the metal plating layer for connection of the active element.

12. The multilayer ceramic substrate according to claim 1, wherein the ceramic substrate is made from Low Temperature Co-fired Ceramics material.