Nonvolatile semiconductor memory

• US 8,227,852 B2
• Filed: 08/15/2007
• Issued: 07/24/2012
• Est. Priority Date: 08/16/2006
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Watanabe, Hiroshi
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Niesz, Jamie C
• Application Number:
  US11/839,156
• Publication Number:
  US 20080042188A1
• Time in Patent Office: 1,805 Days
• Field of Search: 257/315, 257/316, 257/317, 257/E21.209
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory includes a memory cell including, a semiconductor substrate, a first insulating layer on the semiconductor substrate, a floating gate on the first insulating layer, a second insulating layer on the floating gate, and a control gate electrode on the second insulating layer, wherein the floating gate is comprised a first conductive layer which is contact with the first insulating layer, a second conductive layer which is contact with the second insulating layer, and a semiconductor layer between the first and second conductive layers, and each of the first and second conductive layer is a metal layer or a silicide layer.

Claims

1. A nonvolatile semiconductor memory comprising:

a memory cell comprising;

a semiconductor substrate;

a first insulating layer on the semiconductor substrate;

a floating gate on the first insulating layer;

a second insulating layer on the floating gate; and

a control gate electrode on the second insulating layer,

wherein the floating gate comprises a first conductive layer which is in contact with the first insulating layer, a second conductive layer which is in contact with the second insulating layer, and a semiconductor layer between the first and second conductive layers, and each of the first and second conductive layers is a metal layer or a silicide layer.

2. The nonvolatile semiconductor memory according to claim 1, wherein each of the first and second conductive layers is the metal layer.

3. The nonvolatile semiconductor memory according to claim 1, wherein each of the first and second conductive layers is silicide layers.

4. The nonvolatile semiconductor memory according to claim 1, wherein the first conductive layer is the metal layer and the second conductive layer is the silicide layer.

5. The nonvolatile semiconductor memory according to claim 1, wherein the first conductive layer is the silicide layer and the second conductive layer is the metal layer.

6. The nonvolatile semiconductor memory according to claim 1, wherein the metal layer is selected from the group consisting of aluminum, platinum, copper, gold and alloys thereof.

7. The nonvolatile semiconductor memory according to claim 1, wherein the silicide layer is selected from the group consisting of cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, tantalum silicide, and ruthenium silicide.

8. The nonvolatile semiconductor memory according to claim 1, wherein each thickness of the first and second conductive layers is 0.4 nm or more.

9. The nonvolatile semiconductor memory according to claim 1, wherein the semiconductor memory comprising at least two said memory cells adjacent to each other, and a value obtained in such a way that the sum of the thicknesses of the first and second conductive layers is divided by the thickness of the semiconductor layer is smaller than −

0.022 nm<sup>−

1</sup>×

(interval between the floating gates of two memory cells adjacent to each other) +0.24.

10. A nonvolatile semiconductor memory comprising:

a memory cell comprising;

a semiconductor substrate;

a first insulating layer on the semiconductor substrate;

a floating gate on the first insulating layer;

a second insulating layer on the floating gate; and

a control gate electrode on the second insulating layer,

wherein the floating gate comprises a first conductive layer which is in contact with the first insulating layer, a second conductive layer which is in contact with the second insulating layer, and a semiconductor layer having a shape in which a center part is constricted and arranged between the first and second conductive layers, and each of the first and second conductive layers is metal layer or silicide layer.

11. The nonvolatile semiconductor memory according to claim 10, wherein the metal layer comprises one metal selected from the group consisting of aluminum, platinum, copper, gold and an alloy thereof, and the silicide layer is selected from the group consisting of cobalt silicide, nickel silicide, tungsten silicide, titanium silicide, tantalum silicide, and ruthenium silicide.

12. The nonvolatile semiconductor memory according to claim 10, wherein each thickness of the first and second conductive layers is 0.4 nm or more.

13. The nonvolatile semiconductor memory according to claim 10, wherein the semiconductor layer comprises a compound semiconductor including silicon germanium.

14. The nonvolatile semiconductor memory according to claim 10, wherein the semiconductor memory comprises at least two said memory cells adjacent to each other, and a value obtained in such a way that the sum of the thicknesses of the first and second conductive layers is divided by the thickness of the semiconductor layer is smaller than −

0.022 nm<sup>−

1</sup>×

(interval between the floating gates of two memory cells adjacent to each other) +0.24.

15. The nonvolatile semiconductor memory according to claim 10, further comprising diffusion layers in the semiconductor substrate,

wherein the semiconductor layer has side surfaces opposite to the diffusion layers, and each of the side surfaces has said shape.