Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same
First Claim
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1. A semiconductor device, comprising:
- a semiconductor layer of a first conductivity type having a first surface, a second surface, and a mesa region, the mesa region having a top surface adjacent to the layer'"'"'s first surface, a width, and a net doping concentration of the first conductivity type in a center portion of the mesa region;
an electrically insulated electrode disposed in the semiconductor layer and adjacent to the mesa region, the electrically insulated electrode extending from the layer'"'"'s first surface toward the layer'"'"'s second surface, and having at least one side wall and a bottom wall;
a second electrode disposed adjacent to the top surface of the mesa region;
a third electrode electrically coupled to the semiconductor layer; and
wherein a product of the width and the net doping concentration in the center portion of the mesa region is equal to or less than 2.4×
1012 cm−
2.
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Abstract
Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.
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Citations
35 Claims
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1. A semiconductor device, comprising:
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a semiconductor layer of a first conductivity type having a first surface, a second surface, and a mesa region, the mesa region having a top surface adjacent to the layer'"'"'s first surface, a width, and a net doping concentration of the first conductivity type in a center portion of the mesa region; an electrically insulated electrode disposed in the semiconductor layer and adjacent to the mesa region, the electrically insulated electrode extending from the layer'"'"'s first surface toward the layer'"'"'s second surface, and having at least one side wall and a bottom wall; a second electrode disposed adjacent to the top surface of the mesa region; a third electrode electrically coupled to the semiconductor layer; and wherein a product of the width and the net doping concentration in the center portion of the mesa region is equal to or less than 2.4×
1012 cm−
2. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device, comprising:
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a semiconductor layer of a first conductivity type having a first surface, a second surface, a mesa region, and a first net doping concentration of the first conductivity type in a center portion of the mesa region, the mesa region having a top surface adjacent to the layer'"'"'s first surface; an electrically insulated electrode disposed in the semiconductor layer and adjacent to the mesa region, the electrically insulated electrode extending from the layer'"'"'s first surface toward the layer'"'"'s second surface, and having at least one side wall and a bottom wall; a second electrode disposed adjacent to the top surface of the mesa region; a third electrode electrically coupled to the semiconductor layer; and an enhanced doping region disposed in the semiconductor layer having a second net doping concentration of the first conductivity type that is greater than the first net doping concentration of the first conductivity type, the enhanced doping region being disposed adjacent to the bottom wall of the electrically insulated electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of manufacturing a semiconductor device, the method comprising:
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forming one or more trenches into a semiconductor layer of a first conductivity type to define a mesa region having a width, the semiconductor layer having a first surface and a second surface, the mesa region having a top surface adjacent to the layer'"'"'s first surface and a net dopant concentration of a first conductivity type in a center portion of the mesa region, a product of the width and the net dopant concentration being equal to or less than 2.4×
1012 cm−
2;forming a dielectric layer on the side and bottom walls of the one or more trenches; filling the one or more trenches with conductive material to form an electrically insulated electrode disposed in the semiconductor layer and adjacent to the mesa region, the electrically insulated electrode extending from the layer'"'"'s first surface toward the layer'"'"'s second surface, and having at least one side wall and a bottom wall; forming a second electrode that is disposed adjacent to the top surface of the mesa region; and forming a third electrode electrically coupled to the semiconductor layer. - View Dependent Claims (28, 29, 30)
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31. A method of manufacturing a semiconductor device, the method comprising:
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forming one or more trenches into a semiconductor layer of a first conductivity type to define a mesa region having a width, the semiconductor layer having a first surface, a second surface, and a first net concentration of the first conductivity type in a center portion of the mesa region, the mesa region having a top surface adjacent to the layer'"'"'s first surface, each trench having a bottom wall and one or more side walls; implanting a dopant of the first conductivity type into the semiconductor layer at a location of a bottom wall of at least one trench to form an enhanced doping region disposed in the semiconductor layer having a second net doping concentration of the first conductivity type that is greater than the first net doping concentration of the first conductivity type; forming a dielectric layer on the side and bottom walls of the one or more trenches; filling the one or more trenches with electrically conductive material to form at least one electrically insulated electrode disposed in the semiconductor layer and adjacent to the mesa region, the at least one electrically insulated electrode extending from the layer'"'"'s first surface toward the layer'"'"'s second surface, and having at least one side wall and a bottom wall, the enhanced doping region being disposed adjacent to the bottom wall of the at least one electrically insulated electrode; forming a second electrode that is disposed adjacent to the top surface of the mesa region; and forming a third electrode electrically coupled to the semiconductor layer. - View Dependent Claims (32, 33, 34, 35)
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Specification