Striped on-chip inductor
First Claim
1. A sub-100 nanometer process semiconductor inductor comprising:
- a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port;
the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap;
wherein the plurality of line widths, cross-sectional areas and spacing gaps are chosen as a function of a plurality of design rule check rules comprising a chemical mechanical planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps are formed to comply with the chemical mechanical planarization metal ratio rule; and
wherein the inductor is formed in a top chemical mechanical planarization metal layer of a complementary metal oxide semiconductor configured for 10 GHz radio frequencies.
5 Assignments
0 Petitions
Accused Products
Abstract
Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
38 Citations
29 Claims
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1. A sub-100 nanometer process semiconductor inductor comprising:
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a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port; the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap; wherein the plurality of line widths, cross-sectional areas and spacing gaps are chosen as a function of a plurality of design rule check rules comprising a chemical mechanical planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps are formed to comply with the chemical mechanical planarization metal ratio rule; and wherein the inductor is formed in a top chemical mechanical planarization metal layer of a complementary metal oxide semiconductor configured for 10 GHz radio frequencies. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A sub-100 nanometer process semiconductor inductor, comprising:
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a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port; the lines each having a cross-sectional area, a width that is greater than or equal to about 0.8 microns and less than or equal to about 8 microns, and each line is spaced from an adjacent line by a spacing gap that is greater than or equal to about 0.8 microns; and wherein the plurality of line widths, cross-sectional areas and spacing gaps are selected as a function of a plurality of design rule check rules comprising a chemical mechanical planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps are formed to comply with the chemical mechanical planarization metal ratio rule. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An article of manufacture, comprising:
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a computer-readable tangible storage medium having computer readable program code embodied therewith, the computer readable program code comprising instructions that, when executed by a computer processing unit, cause the computer processing unit to; chose line widths, cross-sectional areas and spacing gaps as a function of a plurality of design rule check rules comprising a chemical mechanical planarization metal ratio rule; form a sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port, wherein the plurality of line widths, cross-sectional areas and spacing gaps comply with the chemical mechanical planarization metal ratio rule; wherein the lines each have a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap; and wherein the inductor is formed in a top chemical mechanical planarization metal layer of a complementary metal oxide semiconductor configured for 10 GHz radio frequencies. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. An article of manufacture, comprising:
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a computer-readable tangible storage medium having computer readable program code embodied therewith, the computer readable program code comprising instructions that, when executed by a computer processing unit, cause the computer processing unit to; form a sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port, wherein the plurality of line widths, cross-sectional areas and spacing gaps comply with the chemical mechanical planarization metal ratio rule; wherein the lines each have a cross-sectional area, a width that is greater than or equal to about 0.8 microns and less than or equal to about 8 microns, and each line is spaced from an adjacent line by a spacing gap that is greater than or equal to about 0.8 microns; and wherein the plurality of line widths, cross-sectional areas and spacing gaps are selected as a function of a plurality of design rule check rules comprising a chemical mechanical planarization metal ratio rule, and the plurality of line widths, cross-sectional areas and spacing gaps are formed to comply with the chemical mechanical planarization metal ratio rule. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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Specification