Structures for preventing cross-talk between through-silicon vias and integrated circuits

• US 8,227,902 B2
• Filed: 11/26/2007
• Issued: 07/24/2012
• Est. Priority Date: 11/26/2007
• Status: Active Grant

• Current Assignee: Parabellum Strategic Opportunities Fund LLC (Parabellum Capital LLC)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Chen-Cheng
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US11/945,022
• Publication Number:
  US 20090134500A1
• Time in Patent Office: 1,702 Days
• Field of Search: 257/620, 257/621, 257/659, 257/698, 257/773, 257/774, 257/E23.067, 257/E23.144, 257/E23.145, 257/E23.174, 257/E23.178
• US Class Current: 257/659
• CPC Class Codes: H01L 2223/6688 Mixed frequency adaptations, i.e. for operation at different frequencies
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.

Claims

1. A semiconductor chip comprising:

a through-substrate via (TSV) extending through a semiconductor substrate, the TSV being a signal-carrying TSV;

a device region; and

a cross-talk prevention ring comprising a first portion in a metallization layer over the semiconductor substrate, the first portion encircling the device region, wherein the TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring, the cross-talk prevention ring comprising a conductive material.

2. The semiconductor chip of claim 1 further comprising a seal ring adjacent to edges of the semiconductor chip, wherein the seal ring encircles the cross-talk prevention ring, and wherein the TSV is between the seal ring and the cross-talk prevention ring.

3. The semiconductor chip of claim 2 further comprising a sacrificial ring between the seal ring and the edges of the semiconductor chip.

4. The semiconductor chip of claim 2 further comprising a plurality of TSVs between the seal ring and the cross-talk prevention ring.

5. The semiconductor chip of claim 1, wherein the cross-talk prevention ring encircles an additional TSV.

6. The semiconductor chip of claim 1 further comprising a seal ring adjacent to edges of the semiconductor chip, wherein the cross-talk prevention ring comprises a seal ring extension and a portion of the seal ring.

7. The semiconductor chip of claim 6, wherein the cross-talk prevention ring comprises a corner portion of the seal ring.

8. The semiconductor chip of claim 6, wherein the cross-talk prevention ring comprises an edge and two corner portions of the seal ring.

9. The semiconductor chip of claim 1, wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion is conductive and is electrically connected to the first portion.

10. The semiconductor chip of claim 1, wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion comprises a dielectric material.

11. The semiconductor chip of claim 1, wherein the cross-talk prevention ring is grounded.

12. The semiconductor chip of claim 1 further comprising a plurality of TSVs, each encircled by an additional grounded cross-talk prevention ring.

13. The semiconductor chip of claim 1, further comprising

a seal ring comprising four sides, each being adjacent to an edge of the semiconductor chip, wherein the cross-talk prevention ring is encircled by the seal ring, wherein the cross-talk prevention ring comprises four sides, each being adjacent to one of the sides of the seal ring, wherein the cross-talk prevention ring is grounded, and wherein the TSV is located in a region between the seal ring and the cross-talk prevention ring.

14. The semiconductor chip of claim 13, wherein the region between the seal ring and the cross-talk prevention ring is substantially free from active devices.

15. The semiconductor chip of claim 13 further comprising a plurality of TSVs distributed in the region between the seal ring and the cross-talk prevention ring.

16. The semiconductor chip of claim 13, wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion is conductive and is electrically connected to the first portion.

17. The semiconductor chip of claim 13, wherein the cross-talk prevention ring comprises a second portion in the semiconductor substrate, and wherein the second portion comprises a dielectric material.

18. The semiconductor chip of claim 1, further comprising

a seal ring comprising four sides, each being adjacent to an edge of the semiconductor chip;

and

a seal ring extension comprising a first end and a second end, each physically connected to a portion of the seal ring, wherein the seal ring extension and the seal ring form the cross-talk prevention ring encircling a first region of the semiconductor die, and wherein the first region is substantially free from active devices, the TSV being located in the first region, a second region outside the cross-talk prevention ring comprising active devices.

19. The semiconductor chip of claim 18, wherein the first region further comprises additional TSVs.