Semiconductor device

• US 8,228,158 B2
• Filed: 03/20/2009
• Issued: 07/24/2012
• Est. Priority Date: 04/03/2008
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tsuda, Hiroshi
• Primary Examiner(s): THOMAS, BRADLEY H
• Application Number:
  US12/382,678
• Publication Number:
  US 20090251275A1
• Time in Patent Office: 1,222 Days
• Field of Search: 337/290, 337/292, 337/297, 257/529, 257/665, 257/209, 438/601, 438/132
• US Class Current: 337/292
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has a semiconductor substrate and a first electrical fuse and a second electrical fuse, which are provided on the semiconductor substrate. The first electrical fuse has a first upper layer wire and a first lower layer wire formed in different wire layers, and a via for connecting the first upper layer wire to the first lower layer wire. The second electrical fuse has a second upper layer wire and a second lower layer wire formed in different wire layers, and a via for connecting the second upper layer wire to the second lower layer wire. The semiconductor device has a connection portion for connecting the above described first upper layer wire of the first electrical fuse to the second lower layer wire of the second electrical fuse. The connection portion connects the first electrical fuse and the second electrical fuse in series.

Claims

1. A semiconductor device, comprising:

a substrate; and

a first electrical fuse and a second electrical fuse provided over said substrate, wherein said first electrical fuse comprises;

a first upper layer wire and a first lower layer wire formed in different wire layers; and

a via for connecting said first upper layer wire and said first lower layer wire, wherein said second electrical fuse comprises;

a second upper layer wire and a second lower layer wire formed in different wire layers; and

a via for connecting said second upper layer wire and said second lower layer wire,

wherein the semiconductor device comprises a connection portion, formed in an intermediate layer disposed between the first upper layer wire and the second lower layer wire, for connecting said first upper layer wire of said first electrical fuse to said second lower layer wire of said second electrical fuse, and

wherein said first electrical fuse and said second electrical fuse are connected in series via said connection portion.

2. The semiconductor device according to claim 1, wherein said connection portion comprises a via for connecting said first upper layer wire of said first electrical fuse to said second lower layer wire of said second electrical fuse.

3. The semiconductor device according to claim 1, wherein said first lower layer wire of said first electrical fuse and said second lower layer wire of said second electrical fuse are provided in a same wire layer, and

wherein said first upper layer wire of said first electrical fuse and said second upper layer wire of said second electrical fuse are provided in a same wire layer.

4. The semiconductor device according to claim 2, wherein a plurality of vias, as said connection portion, are provided.

5. The semiconductor device according to claim 2, wherein the vias of said first electrical fuse and said second electrical fuse have a same diameter.

6. The semiconductor device according to claim 5, wherein a diameter of the via of said connection portion is greater than the diameter of the vias of said first electrical fuse and said second electrical fuse.

7. The semiconductor device according to claim 1, wherein a flow-out portion which flows out is formed in one of said first upper layer wire and said first lower layer wire, and a space is created between an other of said first upper layer wire and said first lower layer wire and the via of said first electrical fuse, or in the via of said first electrical fuse, when said first electrical fuse is cut, and

wherein a flow-out portion which flows out is formed in one of said second upper layer wire and said second lower layer wire, and a space is created between an other of said second upper layer wire and said second lower layer wire and the via of said second electrical fuse, or in the via of said second electrical fuse, when said second electrical fuse is cut.

8. The semiconductor device according to claim 7, wherein the via of said first electrical fuse connects an end portion of said first upper layer wire to an end portion of said first lower layer wire, and

wherein the via of said second electrical fuse connects an end portion of said second upper layer wire to an end portion of said second lower layer wire.

9. The semiconductor device according to claim 1, wherein said connection portion abuts an upper surface of the second lower layer wire.

10. The semiconductor device according to claim 1, wherein, in a plan view, said connection portion overlaps with the first upper layer wire and the second lower layer wire.

11. The semiconductor device according to claim 1, further comprising:

an interlayer insulating film that abuts side surfaces of the first upper layer wire and the second upper layer wire.

12. The semiconductor device according to claim 11, further comprising:

another interlayer insulating film that abuts side surfaces of the first lower layer wire and the second lower layer wire.

13. The semiconductor device according to claim 1, wherein the first lower layer wire is connected in series to the second lower layer wire through said connection portion.

14. The semiconductor device according to claim 1, wherein the via of said first electrical fuse abuts a bottom surface of the first upper layer wire.

15. The semiconductor device according to claim 1, further comprising:

an etching prevention film formed on a surface of the second lower layer wire;

an interlayer insulating film formed on an upper surface of the etching prevention film; and

another etching prevention film formed on an upper surface of the interlayer insulating film,

wherein said connection portion is penetrated through said etching prevention film, said interlayer insulating film, and said another etching prevention film.

16. The semiconductor device according to claim 1, wherein, when a voltage is applied between the first lower layer wire and the second upper layer wire, a current flows from the first lower layer wire through the via of said first electrical fuse, the first upper layer wire, the connection portion, the second lower layer wire, the via of said second electrical fuse, and the second upper layer wire, in that order.

17. The semiconductor device according to claim 1, wherein a plurality of ones of the connection portion abuts the lower surface of the first upper layer wire and an upper surface of the second lower layer wire.

18. The semiconductor device according to claim 1, wherein said connection portion abuts a bottom surface of the first upper layer wire.

19. The semiconductor device according to claim 1, wherein the via of said first electrical fuse is directly connected to said first upper layer wire and said first lower layer wire, and the via of said second electrical fuse is directly connected to said second upper layer wire and said second lower layer wire.

20. A semiconductor device, comprising:

a first layer comprising a first lower layer wire and a second lower layer wire;

a second layer comprising a first upper layer wire and a second upper layer wire; and

an intermediate layer disposed over an upper surface of the first layer and below a bottom surface of the second layer, said intermediate layer comprising;

a via connecting said first upper layer wire and said first lower layer wire;

a connection portion connecting said first upper layer wire and said second lower layer wire; and

another via connecting said second upper layer wire and said second lower layer wire,

wherein the connection portion and said via abut a bottom surface of the first upper layer wire, and

wherein said another via abuts a bottom surface of the second upper layer wire and an timer surface of the second lower layer wire such that the first lower layer wire is connected in series to the second lower layer wire through said connection portion.