Sequence and timing control of writing and rewriting pixel memories with substantially lower data rate
First Claim
1. An image display system implemented with a spatial light modulator (SLM) having a plurality of pixel elements to receive and apply image data of multiple bits to display image according to the image data, the image display system further comprising:
- a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in a order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing.
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Abstract
A spatial light modulator driven with binary pulse-width-modulation requires very high data transfer rate to achieve high grayscale. This invention enables to reduce substantially the data transfer rate using non-sequential order of binary bits, wherein the combination of the sequences of binary bits is selected from the combinations which avoid simultaneous writing of multiple rows. The possible number of such combinations is astronomically large and mathematical programs were developed to find right combinations. These results were proposed.
36 Citations
8 Claims
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1. An image display system implemented with a spatial light modulator (SLM) having a plurality of pixel elements to receive and apply image data of multiple bits to display image according to the image data, the image display system further comprising:
a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in a order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
Specification