Memory utilizing oxide nanolaminates

• US 8,228,725 B2
• Filed: 05/28/2010
• Issued: 07/24/2012
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Ahn, Kie Y.
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US12/790,625
• Publication Number:
  US 20100244122A1
• Time in Patent Office: 788 Days
• Field of Search: 365/185.03, 365/185.05, 365/51, 365/63, 365/72, 365/184, 257/324, 257/325, 257/760
• US Class Current: 365/184
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Claims

1. A transistor, comprising:

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator; and

wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is a substantially amorphous metal oxide.

2. The transistor of claim 1, wherein the charge trapping layer includes a transition metal oxide.

3. The transistor of claim 1, wherein the oxide insulator nanolaminate layers include hafnium oxide.

4. A vertical memory cell, comprising:

a vertical transistor extending outwardly from a substrate, the vertical transistor having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is a substantially amorphous transition metal oxide;

a control line coupled to the gate;

a first transmission line formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the first transmission line; and

a second transmission line coupled to the drain region.

5. The memory cell of claim 4, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

6. The memory cell of claim 4, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

7. A vertical memory cell, comprising:

a vertical transistor extending outwardly from a substrate, the vertical transistor having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes nanolaminate charge trapping layers, wherein at least one charge trapping layer is a substantially amorphous metal oxide, at least one nanolaminate layer formed using atomic layer deposition techniques;

a control line coupled to the gate;

a first transmission line formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the first transmission line; and

a second transmission line coupled to the drain region.

8. The memory cell of claim 7, wherein the nanolaminate charge trapping layers includes zirconium oxide.

9. A transistor array, comprising:

a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is a substantially amorphous metal oxide;

a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array;

a number of control lines coupled to the gate of each transistor cell along columns of the transistor array; and

a number of first transmission lines, wherein the first source/drain region of each transistor cell is coupled to the number of first transmission lines along rows of the transistor cells.

10. The transistor array of claim 9, wherein the insulator nanolaminate layers include transition metal oxides.

11. The transistor array of claim 9, wherein the gate insulator of each transistor cell has a thickness of approximately 10 nanometers (nm).

12. A method for forming a transistor device, comprising:

forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;

forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming a plurality of monolayers, including a charge trapping layer, using atomic layer deposition, wherein the charge trapping layer is a substantially amorphous metal oxide; and

forming a gate over the multilayer gate insulator.

13. The method of claim 12, wherein forming the plurality of monolayers includes forming the charge trapping layer from a transition metal oxide.

14. The method of claim 12, wherein forming oxide insulator nanolaminate layers includes forming titanium oxide layers.

15. A vertical memory cell, comprising:

a vertical transistor extending outwardly from a substrate, the vertical transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes at least one amorphous metal oxide charge trapping nanolaminate layer formed using atomic layer deposition techniques;

a first transmission line coupled to the first source/drain region; and

a second transmission line coupled to the second source/drain region.

16. The vertical memory cell of claim 15, wherein the charge trapping nanolaminate layer includes transition metal oxides.

17. The vertical memory cell of claim 15, wherein the charge trapping nanolaminate layer includes tantalum oxide.

18. The vertical memory cell of claim 15, wherein the multilayer gate insulator has a thickness of approximately 10 nanometers (nm).