×

N-channel SONOS non-volatile memory for embedded in logic

  • US 8,228,726 B2
  • Filed: 10/18/2010
  • Issued: 07/24/2012
  • Est. Priority Date: 12/14/2008
  • Status: Active Grant
First Claim
Patent Images

1. A non-volatile memory cell embedded in common logic, the cell comprising:

  • an n-doped layer of silicon;

    a P-well disposed on the n-doped layer; and

    an n-channel Metal Oxide Semiconductor (NMOS) transistor with an Oxide-Nitride-Oxide (ONO) gate dielectric disposed in the P-well, the NMOS transistor comprising;

    a source;

    a drain;

    a channel region disposed between the source and the drain; and

    one of a poly-silicon and a metal control gate disposed on the ONO gate dielectric to result in one of a SONOS and a MONOS transistor, respectively, the control gate being configured to be selectively coupled to a positive bias and one of the source and the drain being configured to be selectively coupled to a negative bias during a program operation, and the positive and negative biases being less than a maximum voltage limit of input/output (I/O) transistors used in the common logic.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×