N-channel SONOS non-volatile memory for embedded in logic
First Claim
1. A non-volatile memory cell embedded in common logic, the cell comprising:
- an n-doped layer of silicon;
a P-well disposed on the n-doped layer; and
an n-channel Metal Oxide Semiconductor (NMOS) transistor with an Oxide-Nitride-Oxide (ONO) gate dielectric disposed in the P-well, the NMOS transistor comprising;
a source;
a drain;
a channel region disposed between the source and the drain; and
one of a poly-silicon and a metal control gate disposed on the ONO gate dielectric to result in one of a SONOS and a MONOS transistor, respectively, the control gate being configured to be selectively coupled to a positive bias and one of the source and the drain being configured to be selectively coupled to a negative bias during a program operation, and the positive and negative biases being less than a maximum voltage limit of input/output (I/O) transistors used in the common logic.
1 Assignment
0 Petitions
Accused Products
Abstract
A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
-
Citations
29 Claims
-
1. A non-volatile memory cell embedded in common logic, the cell comprising:
-
an n-doped layer of silicon; a P-well disposed on the n-doped layer; and an n-channel Metal Oxide Semiconductor (NMOS) transistor with an Oxide-Nitride-Oxide (ONO) gate dielectric disposed in the P-well, the NMOS transistor comprising; a source; a drain; a channel region disposed between the source and the drain; and one of a poly-silicon and a metal control gate disposed on the ONO gate dielectric to result in one of a SONOS and a MONOS transistor, respectively, the control gate being configured to be selectively coupled to a positive bias and one of the source and the drain being configured to be selectively coupled to a negative bias during a program operation, and the positive and negative biases being less than a maximum voltage limit of input/output (I/O) transistors used in the common logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method comprising:
fabricating a non-volatile memory cell along with at least one other device utilizing a single additional gate-dielectric mask, the fabrication process of the non-volatile memory cell comprising; creating an n-doped layer in a silicon substrate; creating a p-well in the n-doped layer; creating an NMOS transistor in the p-well, the NMOS transistor including a source and a drain on either side of a channel region thereof; and
creating an ONO gate dielectric overlying the p-well.- View Dependent Claims (10, 11, 12, 13)
-
14. A method comprising:
-
creating a non-volatile memory cell through; creating an N-well in a P-type silicon substrate; creating a P-well in the N-well; creating an NMOS transistor in the P-well, the NMOS transistor including a source and a drain on either side of a channel region thereof; and creating an ONO gate dielectric overlying the P-well; creating common logic components on the same substrate as the non-volatile memory cell through at least all steps required in a same common logic process; and utilizing a single additional gate-dielectric mask to mask the common logic components to mask deposition of the ONO gate dielectric. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
-
21. An integrated circuit comprising:
-
at least one logic component having a gate; and a non-volatile memory cell coupled to the at least one logic component, the non-volatile memory cell also including a gate, the gate of the at least one logic component and the gate of the non-volatile memory cell each having one of;
a poly-silicon and a metal common single-layer gate structure, the logic component being created on a same substrate as the non-volatile memory cell through at least all steps required in a common logic process, and a single additional gate-dielectric mask being utilized to create the non-volatile memory cell. - View Dependent Claims (22, 23, 24, 25, 26, 27)
-
-
28. A method of fabricating an integrated circuit having common logic and non-volatile memory, the method comprising:
-
creating an n-doped layer in a silicon substrate; creating a p-well in the n-doped layer; creating a source and a drain region for transistors in both the common logic and the non-volatile memory using a common logic process; creating an ONO gate dielectric for the non-volatile memory using a single additional gate-dielectric mask; and utilizing a same logic process to fabricate both the common logic and the non-volatile memory, except for the utilization of the single additional gate-dielectric mask. - View Dependent Claims (29)
-
Specification