Digital signal processing based de-serializer
First Claim
1. An apparatus, comprising:
- a compensation circuitry for processing an analog signal thereby generating a processed analog signal;
an analog to digital converter (ADC) for sampling the processed analog signal thereby generating a plurality of digital samples; and
a digital signal processor (DSP) for;
processing the at least some of the plurality of digital samples in accordance with generating and providing at least one of a first control signal to the compensation circuitry and a second control signal to the ADC; and
performing at least one compensation operation on the plurality of digital samples thereby generating a compensated plurality of digital samples; and
wherein;
operation of the compensation circuitry adaptive based on the first control signal;
operation of the ADC adaptive based on the second control signal; and
at least one of the first control signal and the second control signal based on at least some of the plurality of digital samples.
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Accused Products
Abstract
A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.
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Citations
20 Claims
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1. An apparatus, comprising:
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a compensation circuitry for processing an analog signal thereby generating a processed analog signal; an analog to digital converter (ADC) for sampling the processed analog signal thereby generating a plurality of digital samples; and a digital signal processor (DSP) for; processing the at least some of the plurality of digital samples in accordance with generating and providing at least one of a first control signal to the compensation circuitry and a second control signal to the ADC; and performing at least one compensation operation on the plurality of digital samples thereby generating a compensated plurality of digital samples; and
wherein;operation of the compensation circuitry adaptive based on the first control signal; operation of the ADC adaptive based on the second control signal; and at least one of the first control signal and the second control signal based on at least some of the plurality of digital samples. - View Dependent Claims (2, 3, 4)
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5. An apparatus, comprising:
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a compensation circuitry for processing an analog signal thereby generating a processed analog signal; and an analog to digital converter (ADC) for sampling the processed analog signal thereby generating a plurality of digital samples; and
wherein;operation of the compensation circuitry adaptive based on a first control signal; operation of the ADC adaptive based on a second control signal; and at least one of the first control signal and the second control signal based on at least some of the plurality of digital samples. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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operating a compensation circuitry for processing an analog signal thereby generating a processed analog signal; and operating an analog to digital converter (ADC) for sampling the processed analog signal thereby generating a plurality of digital samples; adapting operation of the compensation circuitry based on a first control signal; and adapting operation of the ADC adaptive based on a second control signal, wherein at least one of the first control signal and the second control signal based on at least some of the plurality of digital samples. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification