Techniques for multi-memory device lifetime management

• US 8,230,164 B2
• Filed: 06/24/2010
• Issued: 07/24/2012
• Est. Priority Date: 11/24/2006
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US12/822,442
• Publication Number:
  US 20110125956A1
• Time in Patent Office: 761 Days
• Field of Search: 711/100, 711/103, 711/154, 711161-162, 711170-172, 711/E12.002
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.

Claims

1. A system comprising:

a controller;

at least one memory device; and

wherein the controller is

enabled to identify at least one aspect associated with a lifetime of each of a plurality of memory device portions of the at least one memory device,

enabled to determine that the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions, and

enabled to, in response to the determination of whether the aspect associated with the lifetime of the first memory device portion storing the first set of data exceeds that of the aspect associated with the lifetime of the second memory device portion, move the first set of data from the first memory device portion to the second memory device portion; and

wherein the first memory device portion and the second memory device portion are portions of a same one of the at least one memory device.

2. The system of claim 1, wherein the lifetime comprises at least one of a desired lifetime, an actual lifetime, and an estimated lifetime.

3. The system of claim 1, wherein the at least one aspect comprises at least one of a period of time, a rate of operations that reduce the lifetime that the at least one aspect is associated with, a total permitted number of the operations that reduce the lifetime that the at least one aspect is associated with, and a duration of the lifetime that the at least one aspect is associated with.

4. The system of claim 1, wherein the at least one aspect comprises a frequency of writing.

5. The system of claim 1, wherein the at least one aspect indicates that the first set of data is more frequently overwritten with respect to a second set of data of the second memory device portion.

6. The system of claim 5, wherein the controller is further enabled to move the first set of data from the first memory device portion to the second memory device portion after a predetermined amount of time.

7. The system of claim 1, wherein the at least one memory device comprises a nonvolatile memory device.

8. The system of claim 7, wherein the nonvolatile memory device comprises at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, a multi-bit per cell NAND flash memory, a multi-level-multi-bit per cell NAND flash, and a large block flash memory.

9. A system comprising:

means for identifying at least one aspect associated with a lifetime of each of a plurality of memory device portions of at least one memory device;

means for determining, at least in part by a controller coupled to a host processor and to the at least one memory device, that the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions; and

means for, in response to the determining, moving the first set of data from the first memory device portion to the second memory device portion; and

wherein the first memory device portion and the second memory device portion are portions of a same one of the at least one memory device.

10. The system of claim 9, wherein the lifetime comprises at least one of a desired lifetime, an actual lifetime, and an estimated lifetime.

11. The system of claim 9, wherein the at least one aspect comprises at least one of a period of time, a rate of operations that reduce the lifetime that the at least one aspect is associated with, a total permitted number of the operations that reduce the lifetime that the at least one aspect is associated with, and a duration of the lifetime that the at least one aspect is associated with.

12. The system of claim 9, wherein the at least one aspect comprises a frequency of writing.

13. The system of claim 9, wherein the at least one aspect indicates that the first set of data is more frequently overwritten with respect to a second set of data of the second memory device portion.

14. The system of claim 13, wherein the means for moving is enabled to move the first set of data from the first memory device portion to the second memory device portion after a predetermined amount of time.

15. The system of claim 9, wherein the at least one memory device comprises a nonvolatile memory device.

16. The system of claim 15, wherein the nonvolatile memory device comprises at least one of a single-bit per cell NOR flash memory, a multi-bit per cell NOR flash memory, a single-bit per cell NAND flash memory, a multi-bit per cell NAND flash memory, a multi-level-multi-bit per cell NAND flash, and a large block flash memory.

17. A computer program product embodied on a tangible computer readable medium, wherein when executed by a computer processor, the computer program product enables functions comprising:

computer code to identify at least one aspect associated with a lifetime of each of a plurality of memory device portions of at least one memory device;

computer code to determine that the aspect associated with the lifetime of a first one of the memory device portions storing a first set of data exceeds that of the aspect associated with the lifetime of a second one of the memory device portions;

computer code to, in response to the determination of whether the aspect associated with the lifetime of the first memory device portion storing the first set of data exceeds that of the aspect associated with the lifetime of the second memory device portion, move the first set of data from the first memory device portion to the second memory device portion; and

wherein the first memory device portion and the second memory device portion are portions of a same one of the at least one memory device.

18. The computer program product of claim 17, wherein the lifetime comprises at least one of a desired lifetime, an actual lifetime, and an estimated lifetime.

19. The computer program product of claim 17, wherein the at least one aspect comprises at least one of a period of time, a rate of operations that reduce the lifetime that the at least one aspect is associated with, a total permitted number of the operations that reduce the lifetime that the at least one aspect is associated with, and a duration of the lifetime that the at least one aspect is associated with.

20. The computer program product of claim 17, wherein the at least one aspect comprises a frequency of writing.

21. The computer program product of claim 17, wherein the at least one aspect indicates that the first set of data is more frequently overwritten with respect to a second set of data of the second memory device portion.

22. The computer program product of claim 21, wherein the functions further comprise computer code to move the first set of data from the first memory device portion to the second memory device portion after a predetermined amount of time.