Administering non-cacheable memory load instructions

• US 8,230,179 B2
• Filed: 05/15/2008
• Issued: 07/24/2012
• Est. Priority Date: 05/15/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kriegel, Jon K., Kuesel, Jamie R.
• Primary Examiner(s): Lee, Chun-Kuan
• Assistant Examiner(s): GEIB, BENJAMIN P
• Application Number:
  US12/121,222
• Publication Number:
  US 20090287885A1
• Time in Patent Office: 1,531 Days
• Field of Search: 711/138, 711/143, 712/225
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

Administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment including a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache. Embodiments of the present invention include receiving, by the cache controller, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable; determining by the cache controller from a cache directory whether the data is cached; if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache'"'"'s state; and if the data is not cached, returning the data from main memory without affecting the write-back cache'"'"'s state.

Claims

1. A method of administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment comprising a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache, the method comprising:

receiving, by the cache controller from a consumer, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable;

determining by the cache controller from a cache directory whether the data is cached;

if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache'"'"'s state; and

if the data is not cached, returning the data from main memory without affecting the write-back cache'"'"'s state.

2. The method of claim 1 wherein the method is applied by the cache controller, to all non-cacheable memory load instructions.

3. The method of claim 1 further comprising marking, by a memory management unit, memory pages with attributes indicating whether to apply the method to non-cacheable memory load instructions for data stored in each page, wherein the method is applied only to non-cacheable memory load instructions for data stored in memory pages marked with the attributes.

4. The method of claim 1 wherein the method is applied to only non-cacheable memory load instructions from particular consumers for which the method is to be applied and the method further comprises:

determining by the cache controller that the consumer is a particular consumer for which the method is to be applied.

5. The method of claim 1 wherein the method is implemented on a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; and

at least one IP block further comprises the hierarchy of memory.

6. The method of claim 5 wherein each IP block comprises a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

7. Apparatus for administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment comprising a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of:

receiving, by the cache controller from a consumer, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable;

determining by the cache controller from a cache directory whether the data is cached;

if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache'"'"'s state; and

if the data is not cached, returning the data from main memory without affecting the write-back cache'"'"'s state.

8. The apparatus of claim 7 wherein the wherein the apparatus is configured to operate in a mode in which the cache controller processes all non-cacheable memory load instructions in a coherent manner without harming performance of a producer.

9. The apparatus of claim 7 further comprising computer program instructions capable of marking, by a memory management unit, memory pages with attributes indicating whether to apply the method to non-cacheable memory load instructions for data stored in each page, wherein the apparatus is configured to operate in a mode in which only non-cacheable memory load instructions for data stored in memory pages marked with the attributes are processed in a coherent manner without affecting the write-back cache'"'"'s state.

10. The apparatus of claim 7 wherein the apparatus is configured to operate in a mode in which only non-cacheable memory load instructions from particular consumers are processed in a coherent manner without affecting the write-back cache'"'"'s state;

and

the apparatus further comprises computer program instructions capable of determining, by the cache controller, that the consumer is a particular consumer.

11. The apparatus of claim 7 further comprising a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein at least one IP block further comprises the hierarchy of memory.

12. The apparatus of claim 11 wherein each IP block comprises a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

13. A computer program product for administering non-cacheable memory load instructions in a computing environment where cacheable data is produced and consumed in a coherent manner without harming performance of a producer, the environment comprising a hierarchy of computer memory that includes one or more caches backed by main memory, the caches controlled by a cache controller, at least one of the caches configured as a write-back cache, the computer program product disposed in a computer-readable recordable signal bearing medium, the computer program product comprising computer program instructions capable of:

receiving, by the cache controller from a consumer, a non-cacheable memory load instruction for data stored at a memory address, the data treated by the producer as cacheable;

determining by the cache controller from a cache directory whether the data is cached;

if the data is cached, returning the data in the memory address from the write-back cache without affecting the write-back cache'"'"'s state; and

if the data is not cached, returning the data from main memory without affecting the write-back cache'"'"'s state.

14. The computer program product of claim 13 wherein the wherein the computer program product is configured to operate in a mode in which the cache controller processes all non-cacheable memory load instructions in a coherent manner without harming performance of a producer.

15. The computer program product of claim 13 further comprising computer program instructions capable of marking, by a memory management unit, memory pages with attributes indicating whether to apply the method to non-cacheable memory load instructions for data stored in each page, wherein the computer program product is configured to operate in a mode in which only non-cacheable memory load instructions for data stored in memory pages marked with the attributes are processed in a coherent manner without affecting the write-back cache'"'"'s state.

16. The computer program product of claim 13 wherein the computer program product is configured to operate in a mode in which only non-cacheable memory load instructions from particular consumers are processed in a coherent manner without affecting the write-back cache'"'"'s state;

and

the computer program product further comprises computer program instructions capable of determining, by the cache controller, that the consumer is a particular consumer.

17. The computer program product of claim 13 wherein the computer program instructions are capable of execution upon a network on chip (‘

NOC’

), the NOC comprising integrated processor (‘

IP’

) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, wherein at least one IP block further comprises the hierarchy of memory.

18. The computer program product of claim 17 wherein each IP block comprises a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.