System and method for providing more logical memory ports than physical memory ports

• US 8,230,182 B2
• Filed: 09/13/2010
• Issued: 07/24/2012
• Est. Priority Date: 03/08/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Teig, Steven, Hutchings, Brad
• Primary Examiner(s): Patel, Hetul
• Application Number:
  US12/881,157
• Publication Number:
  US 20110004734A1
• Time in Patent Office: 680 Days
• Field of Search: 711/149
• US Class Current: 711/149
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Claims

1. A method of mapping a user design with a user design clock cycle to an integrated circuit (IC) for implementing user designs, the method comprising:

receiving a definition of the user design;

identifying a plurality of accesses in a single user design clock cycle period to a plurality of memory ports of a multi-port memory defined in the user design, said single user design clock cycle period specifying a smallest periodic interval that is used in the definition of the user design; and

mapping the plurality of identified accesses to said multi-port memory to a plurality of sequential accesses of a physical port of a physical memory in the IC during multiple periods within said single user design clock cycle period.

2. The method of claim 1, wherein the physical port of said physical memory in the IC is for accessing the physical memory in the IC at least once per period within said single user design clock cycle period.

3. The method of claim 1, wherein a memory port of the plurality of memory ports of the multi-port memory corresponds to both said physical port and a particular period within said single user design clock cycle period.

4. The method of claim 3, wherein the memory port is a first memory port and the particular period is a first particular period, wherein the multi-port memory comprises a second memory port corresponding to both said physical port and a second particular period within said single user design clock cycle period.

5. The method of claim 4, wherein the first memory port is identified by a first logical port number and the second memory port is identified by a second logical port number, wherein a port with a higher logical port number corresponds to a later period within said single user design clock cycle period than a port with a lower port number.

6. The method of claim 4, wherein the first memory port is identified by a first logical port number and the second memory port is identified by a second logical port number, wherein a port with a higher logical port number corresponds to an earlier period within said single user design clock cycle period than a port with a lower port number.

7. The method of claim 1, wherein said plurality of identified accesses is a first plurality of identified accesses, wherein said physical memory comprises at least two physical ports and said physical port is a first physical port of said physical memory, said method further comprising:

identifying a second plurality of accesses in the single user design clock cycle period to the plurality of memory ports of the multi-port memory defined in the user design; and

mapping the second plurality of identified accesses to said multi-port memory to a plurality of sequential accesses of a second physical port of the physical memory in the IC during multiple periods within the single user design clock cycle period.

8. The method of claim 7, wherein the user design comprises (i) a first logical port corresponding to both said first physical port and a first period within said single user design clock cycle period and (ii) a second logical port corresponding to both said second physical port and said first period within said single user design clock cycle period.

9. The method of claim 7, wherein the plurality of memory ports is a first plurality of memory ports, wherein the user design comprises a second plurality of memory ports of said multi-port memory corresponding to the second physical port and said multiple periods within said single user design clock cycle period.

10. A non-transitory computer readable medium storing a computer program for mapping a user design having an associated user design clock cycle to an integrated circuit (IC) that comprises reconfigurable circuits for reconfiguring a plurality of times during each user design clock cycle, said computer program comprising sets of instructions for:

receiving a definition of the user design;

identifying multiple accesses in a single user design clock cycle to a particular number of ports of a multi-port first memory of the user design, said user design clock cycle specifying a smallest periodic interval that is used in the definition of the user design; and

mapping said multiple accesses to said multi-port first memory to a plurality of sequential accesses of a second memory in the IC through a smaller number of ports of the second memory of the IC than the particular number of ports of the multi-port first memory of the user design, each of said plurality of sequential accesses starting before an end of the single user design clock cycle.

11. The non-transitory computer readable medium of claim 10, wherein the single user design clock cycle has only one rising edge and only one falling edge.

12. The non-transitory computer readable medium of claim 10, wherein the reconfigurable circuits reconfigure once in a reconfiguration period, wherein the single user design clock cycle comprises a plurality of reconfiguration periods.

13. The non-transitory computer readable medium of claim 12, wherein a physical port of said second memory is for accessing said second memory at least once per reconfiguration period.

14. The non-transitory computer readable medium of claim 13, wherein a port of the multi-port first memory of the user design corresponds to both a particular port of the second memory and a first reconfiguration period within the single user design clock cycle.

15. The non-transitory computer readable medium of claim 14, wherein the port of the multi-port first memory is a first port, wherein a second port of the multi-port first memory corresponds to both the particular port of the second memory and a second reconfiguration period within the single user design clock cycle.

16. The non-transitory computer readable medium of claim 15, wherein the first port of the multi-port first memory is identified by a first logical port number and the second port of the multi-port first memory is identified by a second logical port number, wherein a port with a higher logical port number corresponds to a later reconfiguration period within said single user design clock cycle than a port with a lower logical port number.

17. The non-transitory computer readable medium of claim 15, wherein the first port of the multi-port first memory is identified by a first logical port number and the second port of the multi-port first memory is identified by a second logical port number, wherein a port with a higher logical port number corresponds to an earlier reconfiguration period within said single user design clock cycle than a port with a lower port number.

18. An integrated circuit (IC) comprising:

a plurality of reconfigurable circuits for implementing a user design by reconfiguring one or more times during each user design clock cycle; and

a semiconductor memory with a physical port for simulating a multi-port memory of the user design by receiving multiple accesses to the physical port during a user design clock cycle, wherein each access of said multiple accesses of the physical port in said user design clock cycle corresponds to one access of one port of said multi-port memory during the user design clock cycle.

19. The IC of claim 18, wherein the physical port is a first physical port, said IC further comprising a second physical port for performing multiple accesses of the semiconductor memory in said user design clock cycle.

20. The IC of claim 18, wherein the plurality of reconfigurable circuits reconfigures once in a reconfiguration period, wherein said user design clock cycle comprises a plurality of reconfiguration periods.

21. The IC of claim 20, further comprising circuits for sending a set of data to said physical port multiple times per user design clock cycle.

22. The IC of claim 20, wherein the port of said multi-port memory corresponds to both said physical port and a first reconfiguration period within the user design clock cycle.

23. The IC of claim 22, wherein the port of said multi-port memory is a first port, wherein the multi-port memory comprises a second port corresponding to both the physical port and a second reconfiguration period within the user design clock cycle.