Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system

• US 8,230,201 B2
• Filed: 04/16/2009
• Issued: 07/24/2012
• Est. Priority Date: 04/16/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): HUISMAN, DAVID J
• Application Number:
  US12/425,057
• Publication Number:
  US 20100269115A1
• Time in Patent Office: 1,195 Days
• Field of Search: None
• US Class Current: 712/220
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism detects a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address. The wake-and-go mechanism creates a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address. The operating system places the thread in a sleep state. Responsive to detecting the event that modifies the data value associated with the target address, the wake-and-go mechanism assigns the wake-and-go instance to a second processing unit within the plurality of processing units. The operating system on the second processing unit places the thread in a non-sleep state.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

responsive to a first wake-and-go mechanism associated with a first processing unit within a plurality of processing units detecting a thread running on the first processing unit that is waiting for an event that modifies a data value associated with a target address, placing the thread in a sleep state;

creating a wake-and-go instance for the thread comprising the target address and a thread identifier associated with the thread;

assigning the wake-and-go instance to a second processing unit within the plurality of processing units;

storing, by a second wake-and-go mechanism associated with the second processing unit, the wake-and-go instance in a wake-and-go storage array associated with the second processing unit; and

responsive to the second wake-and-go mechanism detecting the event that modifies the data value associated with the target address, placing the thread in a non-sleep state,

wherein placing the thread in a non-sleep state comprises;

identifying a third processing unit within the plurality of processing units that has a lowest processor utilization within the plurality of processing units or a lowest priority thread running within the plurality of processing units; and

placing the thread in a run queue of the third processing unit.

2. The method of claim 1, wherein the third processing unit has the lowest priority thread running within the plurality of processing units and wherein placing the thread in a non-sleep state on the third processing unit comprises placing the lowest priority thread in a sleep state on the third processing unit.

3. The method of claim 1, wherein assigning the wake-and-go instance to the second processing unit comprises transferring the wake-and-go instance from the first wake-and-go mechanism to the second wake-and-go mechanism.

4. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address on a bus is used to address the content addressable memory.

5. The method of claim 4, wherein responsive to detecting the event that modifies the data value associated with the target address, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

6. The method of claim 1, wherein assigning the wake-and-go instance to the second processing unit comprises:

identifying the second processing unit from the plurality of processing units based on a number of wake-and-go instances in the wake-and-go storage array associated with the second processing unit.

7. The method of claim 1, wherein placing the thread in a sleep state comprises storing thread state information of the thread in a thread state storage, wherein the wake-and-go instance comprises a thread state pointer referencing the thread state information in the thread state storage, and wherein placing the thread in a non-sleep state comprises restoring the thread state information using the thread state pointer and placing the thread in a run queue of the third processing unit.

8. A data processing system, comprising:

a plurality of processing units;

a first wake-and-go mechanism associated with a first processing unit within the plurality of processing units;

a second wake-and-go mechanism associated with a second processing unit within the plurality of processing units; and

a wake-and-go storage array associated with the second processing unit,

wherein the first wake-and-go mechanism is configured to;

responsive to detecting a thread running on the first processing unit that is waiting for an event that modifies a data value associated with a target address, place the thread in a sleep state;

create a wake-and-go instance for the thread comprising the target address and a thread identifier associated with the thread; and

assign the wake-and-go instance to the second processing unit;

wherein the second wake-and-go mechanism is configured to;

store the wake-and-go instance in the wake-and-go storage array; and

responsive to the second wake-and-go mechanism detecting the event that modifies the data value associated with the target address, place the thread in a non-sleep state;

wherein placing the thread in a non-sleep state comprises;

identifying a third processing unit within the plurality of processing units that has a lowest processor utilization within the plurality of processing units or a lowest priority thread running within the plurality of processing units; and

placing the thread in a run queue of the third processing unit.

9. The data processing system of claim 8, wherein the third processing unit has the lowest priority thread running within the plurality of processing units and wherein placing the thread in a non-sleep state on the third processing unit comprises placing the lowest priority thread in a steep state on the third processing unit.

10. The data processing system of claim 8, wherein assigning the wake-and-go instance to the second processing unit comprises transferring the wake-and-go instance from the first wake-and-go mechanism to the second wake-and-go mechanism.

11. The data processing system of claim 8, wherein the wake-and-go storage array is a content addressable memory and an address on a bus is used to address the content addressable memory.

12. The data processing system of claim 11, wherein responsive to detecting the event that modifies the data value associated with the target address, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

13. The data processing system of claim 8, wherein the first wake-and-go mechanism is a hardware component within the first processing unit and wherein the second wake-and-go mechanism is a hardware component within the second processing unit.

14. A computer program product comprising a non-transitory computer readable medium storing a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

responsive to a first wake-and-go mechanism associated with a first processing unit within a plurality of processing units detecting a thread running on the first processing unit that is waiting for an event that modifies a data value associated with a target address, place the thread in a sleep state;

create a wake-and-go instance for the thread comprising the target address and a thread identifier associated with the thread;

assign the wake-and-go instance to a second processing unit within the plurality of processing units;

store the wake-and-go instance in a wake-and-go storage array associated with the second processing unit; and

responsive to a second wake-and-go mechanism associated with the second processing unit detecting the event that modifies the data value associated with the target address, place the thread in a non-sleep state,

wherein placing the thread in a non-sleep state comprises;

identifying a third processing unit within the plurality of processing units that has a lowest processor utilization within the plurality of processing units or a lowest priority thread running within the plurality of processing units; and

placing the thread in a run queue of the third processing unit.

15. The computer program product of claim 14, wherein assigning the wake-and-go instance to the second processing unit comprises:

identifying the second processing unit from the plurality of processing units based on a number of wake-and-go instances in the wake-and-go storage array associated with the second processing unit.

16. The computer program product of claim 14, wherein placing the thread in a sleep state comprises storing thread state information of the thread in a thread state storage, wherein the wake-and-go instance comprises a thread state pointer referencing the thread state information in the thread state storage, and wherein placing the thread in a non-sleep state comprises restoring the thread state information using the thread state pointer and placing the thread in a run queue of the third processing unit.