Apparatus and method for condensing trace information in a multi-processor system

• US 8,230,202 B2
• Filed: 03/31/2008
• Issued: 07/24/2012
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Berg, Thomas Benjamin, Kinter, Ryan C., Thekkath, Radhika, Patwardhan, Jaidev Prasad
• Primary Examiner(s): FENNEMA, ROBERT E
• Application Number:
  US12/060,204
• Publication Number:
  US 20090249045A1
• Time in Patent Office: 1,576 Days
• Field of Search: None
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.

Claims

1. A non-transitory computer readable storage medium with executable instructions to characterize a coherency controller, comprising executable instructions to define:

ports to receive processor trace information from a plurality of processors, wherein the processor trace information from each processor includes a processor identity and a condensed coherence indicator derived as a function of a processor synchronization signal and a shared memory miss signal, wherein processor synchronization signals define synchronization frames, wherein within a single synchronization frame with multiple memory miss signals, the condensed coherence indicator is incremented only once per synchronization frame, in response to the first memory miss signal of the multiple memory miss signals; and

circuitry to produce a trace stream with trace metrics and condensed coherence indicators.

2. The non-transitory computer readable storage medium of claim 1 wherein the circuitry includes a serialized request handler to provide global transaction ordering of the trace information, wherein the serialized request handler distinguishes coherent memory requests from non-coherent memory requests.

3. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics including a source processor.

4. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics including a serialized command.

5. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics including stall information.

6. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics including the address of a request being traced.

7. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics including a target address.

8. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics in a format specifying a source processor, a coherence indicator, a command and an address target.

9. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics in a format specifying a source processor, a coherence indicator, a command, an address target, and a serialize request handler wait time.

10. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics in a format specifying a source processor, a coherence indicator, a command, an address target and a request address.

11. The non-transitory computer readable storage medium of claim 2 wherein the serialized request handler produces trace metrics in a format specifying a source processor, a coherence indicator, a command, an address target, a request address and a serialize request handler wait time.

12. The non-transitory computer readable storage medium of claim 1 wherein the circuitry includes an intervention unit to send coherent memory requests to the plurality of processors, receive coherent memory responses from the plurality of processors and generate intervention unit trace metrics including a coherence indicator, wherein the intervention unit receives the coherent memory requests from a serialized request handler that distinguishes coherent memory requests from non-coherent memory requests.

13. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including a source processor.

14. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including a bit vector of intervention port responses.

15. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including a global intervention state for a cache line.

16. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including a transaction cancelled indicator.

17. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics indicating that an intervention will cause a cancelled store condition to fail.

18. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics indicating that an intervention will cause a future store condition to fail.

19. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including transaction delay information.

20. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces trace intervention unit trace metrics including stall cause information.

21. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces intervention unit trace metrics in a format specifying a source processor, a coherence indicator, a vector of intervention port responses, a global intervention cache line state, a source condition failure command, and a previous source condition failure indication.

22. The non-transitory computer readable storage medium of claim 12 wherein the intervention unit produces intervention unit trace metrics in a format specifying a source processor, a coherence indicator, a vector of intervention port responses, a global intervention cache line state, a source condition failure command, a previous source condition failure indication, an intervention unit wait time, and a stall cause indicator.

23. The non-transitory computer readable storage medium of claim 1 wherein the circuitry selectively generates a trace buffer overflow indicator.

24. The non-transitory computer readable storage medium of claim 1 wherein the circuitry supports hardware trace breakpoints.

25. The non-transitory computer readable storage medium of claim 1 wherein the circuitry supports the storage of selective trace information in trace memory.

26. The non-transitory computer readable storage medium of claim 25 wherein the selective trace information is selected from a special condition, a trigger, a breakpoint and a trace control block break in tracing.