Method of partitioning an algorithm between hardware and software
First Claim
Patent Images
1. A computer program product for partitioning an algorithm between hardware and software comprising:
- a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising;
computer readable program code to accept a user defined algorithm specified in a source code;
computer readable program code to identify worker methods and feature extraction methods within the user defined algorithm, wherein the feature extraction methods comprise methods selected from the group consisting of;
generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations;
computer readable program code to replace worker methods in the source code with hardware logic;
computer readable program code to replace feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic;
computer readable program code to output an FPGA programming specification of the hardware logic and interface libraries; and
computer readable program code to program an FPGA in response to the FPGA programming specification.
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Abstract
A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.
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Citations
16 Claims
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1. A computer program product for partitioning an algorithm between hardware and software comprising:
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a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising; computer readable program code to accept a user defined algorithm specified in a source code; computer readable program code to identify worker methods and feature extraction methods within the user defined algorithm, wherein the feature extraction methods comprise methods selected from the group consisting of;
generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations;computer readable program code to replace worker methods in the source code with hardware logic; computer readable program code to replace feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic; computer readable program code to output an FPGA programming specification of the hardware logic and interface libraries; and computer readable program code to program an FPGA in response to the FPGA programming specification. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer implemented method of programming a field programmable gate array (FPGA) with an algorithm by partitioning the algorithm between hardware and software, the method comprising:
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accepting a user defined algorithm specified in source code; identifying, by an analyzer module, worker methods and feature extraction methods within the user defined algorithm; replacing, by a mapper module, worker methods in the source code with hardware logic; replacing, by the mapper module, feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, wherein the feature extraction methods comprise methods selected from the group consisting of;
generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations;generating a FPGA programming specification of the hardware logic and interface libraries; and programming at least one target FPGA using the FPGA programming specification. - View Dependent Claims (16)
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Specification