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Method for manufacturing and testing an integrated electronic circuit

  • US 8,232,113 B2
  • Filed: 05/20/2009
  • Issued: 07/31/2012
  • Est. Priority Date: 05/22/2008
  • Status: Active Grant
First Claim
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1. A method for manufacturing and for testing an integrated circuit, comprising the steps of:

  • forming, on the upper portion of the integrated circuit, a passivation layer comprising openings at the level of metal tracks of an interconnect stack of the integrated circuit;

    forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit;

    testing the integrated circuit by bringing test tips in contact with the second pads;

    depositing a multiple-layer conductive stack, for connection with conductive bumps, on the upper portion of the intergrated circuit; and

    etching the multiple-layer stack, except above the first pads, said track sections being of a material such that said etching also removes said track sections, whereby the first and second pads are disconnected, and wherein etching disconnects the second pads from the intergrated circuit.

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