Method for manufacturing and testing an integrated electronic circuit

• US 8,232,113 B2
• Filed: 05/20/2009
• Issued: 07/31/2012
• Est. Priority Date: 05/22/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics Grenoble 2 SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Coffy, Romain
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US12/990,684
• Publication Number:
  US 20110092000A1
• Time in Patent Office: 1,168 Days
• Field of Search: 438/14, 438/15, 438/612, 438/613, 257/E21.521
• US Class Current: 438/14
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

Claims

1. A method for manufacturing and for testing an integrated circuit, comprising the steps of:

forming, on the upper portion of the integrated circuit, a passivation layer comprising openings at the level of metal tracks of an interconnect stack of the integrated circuit;

forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit;

testing the integrated circuit by bringing test tips in contact with the second pads;

depositing a multiple-layer conductive stack, for connection with conductive bumps, on the upper portion of the intergrated circuit; and

etching the multiple-layer stack, except above the first pads, said track sections being of a material such that said etching also removes said track sections, whereby the first and second pads are disconnected, and wherein etching disconnects the second pads from the intergrated circuit.

2. The method of claim 1, further comprising, after the step of etching of the multiple-layer conductive stack, forming conductive bumps on remaining portions of the multiple-layer stack.

3. The method of claim 1, wherein the first and second pads comprise several layers, wherein at least one of said layers of the first pads being not removed at the same time as the conductive track sections.

4. The method of claim 1, wherein the conductive track sections and a first layer of the multiple-layer stack, in contact with the first pads, comprise aluminum.

5. The method of claim 1, wherein the multiple-layer stack comprises three layers.

6. The method of claim 1, wherein the multiple-layer stack comprises:

a first layer, in contact with the first pad, is made of a material selected from the group consisting of aluminum, titanium, titanium and tungsten alloys, chromium, tantalum, silver, and gold;

a second layer, disposed on the first layer, is made of a material selected from the group consisting of vanadium/nickel, titanium nitride, tantalum nitride, nickel, vanadium, chromium, and copper; and

a third layer, disposed on the second layer, is made of a material selected from the group consisting of copper, palladium, gold, and silver.

7. The method of claim 1, wherein the first pads have a hexagonal shape.

8. The method of claim 1, wherein the material of the passivation layer is selected from the group consisting of benzocyclobutene, silicon nitride, and polyimide.

9. The method of claim 1, wherein the conductive track section is formed on the passivation layer.

10. The method of claim 2 further comprising cutting up the integrated circuit into chips.

11. A method for manufacturing an integrated circuit comprising:

forming a connection pad disposed on the integrated circuit and connected with a metal track formed in the integrated circuit;

forming a test pad disposed on the integrated circuit;

forming a conductive track section disposed on the integrated circuit and connecting the connection and test pads; and

etching the integrated circuit, wherein etching the integrated circuit removes the conductive track section, wherein removing the conductive track section disconnects the test pad and the integrated circuit.

12. The method of claim 11, prior to the step of etching the integrated circuit, further comprising bringing a testing tip into contact with the test pad.

13. The method of claim 11, prior to the step of etching the integrated circuit, forming a mask at least above the connection pad.

14. The method of claim 11, wherein removing the conductive track section disconnects the connection and test pads.

15. The method of claim 11, wherein etching the integrated circuit removes the test pad.

16. The method of claim 11 further comprising forming a multi-layer conductive stack on the connection pad, test pad, and conductive track section.

17. The method of claim 16, wherein etching removes a portion of the multi-layer conductive stack.

18. The method of claim 17, wherein etching the integrated circuit comprises etching the conductive track section and at least one layer of the multi-layer conductive stack simultaneously.

19. A method for manufacturing and testing of an integrated circuit comprising:

forming a passivation layer on an upper portion of the integrated circuit with an opening located above and at a level of a metal track formed in the integrated circuit;

forming a first pad in the at least one opening, a second pad on the passivation layer, and a conductive track section connecting the first and second pads;

bringing a testing tip into contact with the second pad;

depositing a multiple-layer conductive stack on the upper portion of the integrated circuit; and

etching the multiple-layer conductive stack, except above the first pad, wherein said etching also removes said conductive track section, wherein said etching disconnects the second pad and the integrated circuit.