Silicon device on Si:C-OI and SGOI and method of manufacture
First Claim
1. A structure, comprising:
- shallow trench isolation (STI) in a substrate;
a first material and a second material on the substrate mixed to form a first island and second island at a nFET region and a pFET region, respectively; and
a layer of material on the first island and the second island having a lattice constant different than the first island and the second island, wherein the STI relaxes and facilitates the relaxation of the first island and the second island, and a first portion of the layer of material acts as a strained channel for a nFET device and a second portion of the layer of material acts as a strained channel for a pFET device.
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Abstract
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
162 Citations
20 Claims
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1. A structure, comprising:
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shallow trench isolation (STI) in a substrate; a first material and a second material on the substrate mixed to form a first island and second island at a nFET region and a pFET region, respectively; and a layer of material on the first island and the second island having a lattice constant different than the first island and the second island, wherein the STI relaxes and facilitates the relaxation of the first island and the second island, and a first portion of the layer of material acts as a strained channel for a nFET device and a second portion of the layer of material acts as a strained channel for a pFET device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor structure, comprising:
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a substrate comprising a buried insulator layer; a relaxed shallow trench isolation of high temperature stable amorphous material formed in the substrate and contacting the buried insulator layer; a first island of thermally annealed mixed material formed in the substrate at a pFET region and contacting the buried insulator layer; a second island of thermally annealed mixed material formed in the substrate at an nFET region and contacting the buried insulator layer; and a strained Si layer formed on and contacting at least one of the first island and the second island. - View Dependent Claims (17)
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18. A semiconductor structure, comprising:
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a substrate; a relaxed shallow trench isolation of high temperature stable amorphous material formed in the substrate; a first island of thermally annealed mixed material formed in the substrate at a pFET region; a second island of thermally annealed mixed material formed in the substrate at an nFET region; and a strained Si layer formed on at least one of the first island and the second island, wherein one of; the first island and the second island is comprised substantially of a mixed material of relaxed SiGe, the first island and the second island is comprised substantially of a mixed material of relaxed Si;
C, andthe first island is comprised substantially of SiGe and the second island is comprised substantially of Si;
C. - View Dependent Claims (19, 20)
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Specification