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Silicon device on Si:C-OI and SGOI and method of manufacture

  • US 8,232,153 B2
  • Filed: 06/04/2007
  • Issued: 07/31/2012
  • Est. Priority Date: 11/19/2003
  • Status: Active Grant
First Claim
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1. A structure, comprising:

  • shallow trench isolation (STI) in a substrate;

    a first material and a second material on the substrate mixed to form a first island and second island at a nFET region and a pFET region, respectively; and

    a layer of material on the first island and the second island having a lattice constant different than the first island and the second island, wherein the STI relaxes and facilitates the relaxation of the first island and the second island, and a first portion of the layer of material acts as a strained channel for a nFET device and a second portion of the layer of material acts as a strained channel for a pFET device.

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