Process for chip capacitive coupling

• US 8,232,194 B2
• Filed: 10/14/2011
• Issued: 07/31/2012
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/273,917
• Publication Number:
  US 20120034739A1
• Time in Patent Office: 291 Days
• Field of Search: 438/618, 438/675, 257/E21.575
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1358 being stacked
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Claims

1. A method comprising:

providing a contact on a first surface of a semiconductor material;

creating a via that extends from a second surface of the semiconductor material through a portion of the semiconductor material, wherein the via has a depth sufficient to bring the via into proximity with, but physically spaced apart from, the contact; and

introducing an electrically-conductive material into the via, wherein the contact and the electrically-conductive material are spaced sufficiently apart such that a signal may capacitively propagate between the contact and the electrically-conductive material, and wherein there is no direct electrical connection between the contact and the electrically-conductive material.

2. The method of claim 1, wherein the semiconductor material comprises a doped semiconductor material, and wherein said creating a via comprises extending the via through at least a portion of a substrate located adjacent the semiconductor material.

3. The method of claim 1, further comprising connecting the electrically-conductive material to a signal source.

4. The method of claim 1, further comprising introducing an electrically-insulating material into the via prior to said introducing an electrically-conductive material into the via, wherein the electrically-insulating material is configured to isolate the electrically -conductive material from the semiconductor material.

5. The method of claim 1, wherein said introducing an electrically-conductive material into the via comprises forming a coaxial conductor within the via, wherein the coaxial conductor includes a first electrical conductor bounded about its periphery by a first insulator, and wherein the first insulator is bounded about periphery by a second electrical conductor.

6. The method of claim 5, wherein, prior to said introducing an electrically-conductive material into the via, the method further comprises introducing an electrically-insulating material into the via about the periphery of the via, thereby electrically isolating the second electrical conductor from the semiconductor material.

7. The method of claim 1, wherein said introducing an electrically-conductive material into the via comprises forming a triaxial conductor within the via, wherein the triaxial conductor includes a first electrical conductor bounded about its periphery by a first insulator, wherein the first insulator is bounded about its periphery by a second electrical conductor, wherein the second electrical conductor is bounded about its periphery by a second insulator, and wherein the second insulator is bounded about its periphery by a third electrical conductor.

8. The method of claim 7, wherein, prior to said introducing an electrically-conductive material into the via, the method further comprises introducing an electrically insulating material into the via about the periphery of the via, thereby electrically isolating the third electrical conductor from the semiconductor material.

9. The method of claim 1, wherein the semiconductor material comprises at least a portion of a first semiconductor chip, the method further comprising stacking the first semiconductor chip onto a second semiconductor chip so that the electrically-conductive material is proximate a device pad of the second semiconductor chip, thereby forming a path for the signal to be propagated between the electrically-conductive material and the device pad of the second semiconductor chip.

10. The method of claim 9, further comprising joining a third semiconductor chip with the first semiconductor chip, wherein the third semiconductor chip has a signal conductor, and wherein the signal conductor is coupled the device pad of the second semiconductor chip.

11. The method of claim 1, wherein the semiconductor material comprises at least a portion of a first semiconductor chip, the method further comprising:

forming a second semiconductor chip according to the method of claim 1; and

stacking the first and second semiconductor chips so that the electrically-conductive material of one of the first or second semiconductor chips abuts the device pad of the other of the first or second semiconductor chips, wherein the stacked first and second semiconductor chips form an integrated unit.

12. The method of claim 11, further comprising:

forming a third semiconductor chip according to the method of claim 1; and

stacking the third semiconductor chip onto the integrated unit so that the electrical conductor of the third semiconductor chip is proximate to, but does not physically contact, an exposed device pad of the integrated unit.

13. The method of claim 11, further comprising:

forming a third semiconductor chip according to the method of claim 1; and

stacking the third semiconductor chip onto the integrated unit so that the device pad of the third semiconductor chip abuts an exposed electrically-conductive material of the integrated unit.

14. The method of claim 1, wherein at least a portion of the semiconductor material is disposed between the contact and the electrically-conductive material.

15. A method comprising:

providing a first contact on a first surface of a first semiconductor material of a first semiconductor chip;

creating a via that extends from a second surface of the first semiconductor material through a portion of the first semiconductor material;

introducing a first electrically-conductive material into the via, wherein the first contact and the first electrically-conductive material are not in direct electrical contact and are spaced sufficiently apart such that a signal may capacitively propagate between the first contact and the first electrically-conductive material;

stacking a second semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip includes a second contact; and

electrically connecting the second contact to the first electrically-conductive material.

16. The method of claim 15, wherein the first semiconductor material comprises a doped semiconductor material, and wherein said creating a via comprises extending the via through at least a portion of a substrate located adjacent the first semiconductor material.

17. The method of claim 15, further comprising connecting the first electrically-conductive material to a signal source.

18. The method of claim 15, further comprising joining a third semiconductor chip to the first semiconductor chip, wherein the third semiconductor chip comprises a signal conductor, and wherein the signal conductor is coupled to the first contact of the first semiconductor chip.

19. The method of claim 15, wherein the stacked first and second semiconductor chips form an integrated unit.

20. The method of claim 19, further comprising stacking a third semiconductor chip onto the integrated unit, wherein the third semiconductor chip includes a third electrically-conductive material, and wherein the third electrically-conductive material is proximate to, but does not physically contact, an exposed contact of the integrated unit.

21. The method of claim 19, further comprising stacking a third semiconductor chip onto the integrated unit, wherein the third semiconductor chip includes a third electrically-conductive material, and wherein the third electrically-conductive material abuts an exposed contact of the integrated unit,

22. The method of claim 15, wherein the second semiconductor chip comprises a second electrically-conductive material not in direct electrical contact with and spaced apart from the second contact by a distance configured to allow the signal to capacitively propagate between the second contact and the second electrically-conductive material.

23. The method of claim 22, further comprising electrically connecting a third contact of a third semiconductor chip to the second electrically-conductive material.

24. The method of claim 15, wherein said introducing a first electrically-conductive material into the via, comprises forming a coaxial conductor within the via, wherein the coaxial conductor includes a first electrical conductor bounded about its periphery by a first insulator, and wherein the first insulator is bounded about its periphery by a second electrical conductor.

25. The method of claim 24, wherein, prior to said introducing a first electrically-conductive material into the via, the method further comprises introducing an electrically-insulating material into the via about the periphery of the via, thereby electrically isolating the second electrical conductor from the first semiconductor material.

26. The method of claim 15, wherein said introducing a first electrically-conductive material into the via comprises forming a triaxial conductor within the via, wherein the triaxial conductor includes a first electrical conductor bounded about its periphery by a first insulator, wherein the first insulator is bounded about its periphery by a second electrical conductor, wherein the second electrical conductor is bounded about its periphery by a second insulator, and wherein the second insulator is bounded about its periphery by a third electrical conductor,

27. The method of claim 26, wherein, prior to said introducing a first electrically-conductive material into the via, the method further comprises introducing an electrically-insulating material into the via about the periphery of the via, thereby electrically isolating the third electrical conductor from the first semiconductor material.