Schemes for forming barrier layers for copper in interconnect structures

• US 8,232,201 B2
• Filed: 05/25/2011
• Issued: 07/31/2012
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US13/115,161
• Publication Number:
  US 20110223762A1
• Time in Patent Office: 433 Days
• Field of Search: 257/E21.199, 257/E21.584, 438/627, 438/630, 438/643, 438/653, 438/664, 438/687
• US Class Current: 438/653
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate;

forming a low-k dielectric layer over the substrate;

forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer;

forming a first barrier layer lining the opening;

embedding a conductive wiring in a remaining portion of the opening;

recessing a top edge of the first barrier layer to form a recess, wherein portions of sidewalls of the conductive wiring are exposed; and

forming a second barrier layer covering a top surface and exposed sidewalls of the conductive wiring, wherein the second barrier layer does not extend over the low-k dielectric layer.

2. The method of claim 1, wherein the first barrier layer comprises a metal that can be silicided.

3. The method of claim 2, wherein the metal comprises a material selected from the group consisting essentially of cobalt, nickel, and combinations thereof.

4. The method of claim 1, wherein the first barrier layer is free from cobalt and nickel.

5. The method of claim 1, wherein the conductive wiring comprises copper.

6. The method of claim 1, wherein the step of forming the second barrier layer comprises electrochemical plating.

7. The method of claim 1, wherein the forming the second barrier layer further comprises thermal soaking the conductive wiring in a carbon-containing silane-based process gas, wherein the thermal soaking occurs in a non-plasma environment.

8. The method of claim 7, wherein the carbon-containing same-based process gas comprises SiH3(CH3)1(1MS), SiH2(CH3)2(2MS), 3MS or combinations thereof.

9. A method of forming a semiconductor structure, the method comprising:

forming an opening in a dielectric layer;

forming a barrier layer within the opening;

forming a conductive material within the opening, the conductive material having a planar top surface extending across an entire width of the conductive material;

removing a portion of the barrier layer to expose a sidewall of the conductive material; and

thermal soaking the planar top surface of the conductive material and the barrier layer in a carbon-containing silane-based process gas to form a silicide layer over the conductive material, over the barrier layer, and along the sidewall.

10. The method of claim 9, wherein the exposing the conductive material and the barrier layer to a carbon-containing silane-based process gas further comprises exposing the conductive material and the barrier layer to silane.

11. The method of claim 9, wherein the forming the barrier layer further comprises forming a layer of cobalt-containing material.

12. The method of claim 9, wherein the forming the barrier layer further comprises forming a layer of nickel.

13. The method of claim 9, wherein the forming the barrier layer further comprises forming a layer of material selected from the group consisting essentially of Ti, TiN, Ta, TaN, CoP, CoB, CoWP, CoWB, NiWP, CoSnP, NiWB, CuSi, ZrN, NiMoP, and combinations thereof.

14. The method of claim 9, wherein the forming the conductive material further comprises forming a layer of copper.

15. The method of claim 9, wherein the removing the portion of the barrier layer removes greater than about 5 percent of a thickness of the conductive material.

16. A method of manufacturing a semiconductor structure, the method comprising:

forming a dielectric layer over a substrate;

removing a portion of the dielectric layer to form an opening sidewalls;

lining the sidewalls with a barrier layer;

filling the opening with a conductive material;

planarizing the dielectric layer, the barrier layer, and the conductive material;

removing a first portion of the barrier layer after the planarizing without removing the conductive material, the removing the portion of the barrier layer exposing sidewalls of the conductive material, wherein the sidewalls of the conductive material have at least a second portion that is perpendicular to the substrate; and

forming a second barrier layer over the conductive material, over the barrier layer, and along the second portion of the conductive material.

17. The method of claim 16, wherein the forming the second barrier layer further comprises thermal soaking the conductive material and the barrier layer in a carbon-containing silane-based process gas to form a silicide layer over the conductive material and the barrier layer.

18. The method of claim 17, wherein the forming the thermal soaking occurs in a plasma environment.

19. The method of claim 16, wherein the forming the barrier layer further comprises forming a layer of cobalt-containing material.

20. The method of claim 16, wherein the forming the barrier layer further comprises forming a layer of nickel.