Spacer linewidth control

• US 8,232,215 B2
• Filed: 11/20/2009
• Issued: 07/31/2012
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Culp, James A., Gambino, Jeffrey P., Ellis-Monaghan, John J., Peterson, Kirk D., Rankin, Jed H.
• Primary Examiner(s): Vinh, Lan
• Application Number:
  US12/622,557
• Publication Number:
  US 20100261351A1
• Time in Patent Office: 984 Days
• Field of Search: 438/706, 438/710, 438/714, 438/723, 438/725, 438/734, 438/736, 438/594, 438/595, 438/737, 216/72, 216/81
• US Class Current: 438/734
• CPC Class Codes: H01L 21/31144 using masks

Abstract

A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Claims

1. A method for fabricating a microelectronic structure comprising:

forming upon a substrate that includes a plurality of evenly spaced topographic features a conformal spacer material layer;

forming upon the conformal spacer material layer a conformal resist layer;

differentially exposing and developing the conformal resist layer over different topographic features to leave remaining a differential thickness resist residue layer upon the conformal spacer material layer over the different topographic features; and

sequentially etching the differential thickness resist residue layer and the conformal spacer material layer to provide different width spacers in direct contact with sidewalls of the different topographic features.

2. The method of claim 1 wherein the conformal resist layer comprises a positive resist material.

3. The method of claim 1 wherein the conformal resist layer comprises a negative resist material.

4. The method of claim 1 wherein the differentially exposing and developing uses a grey scale mask.

5. The method of claim 1 wherein the differentially exposing and developing uses separate binary masks.

6. The method of claim 1 wherein the substrate comprises a semiconductor substrate.

7. The method of claim 6 wherein the topographic features comprise gates within field effect devices.

8. The method of claim 7 wherein the conformal spacer material layer comprises a dielectric material.

9. A method for fabricating a microelectronic structure comprising:

masking a lesser thickness portion of a spacer material layer that is in direct contact with a plurality of narrowly spaced topographic features within a structure that includes;

the plurality of narrowly spaced topographic features and a plurality of widely spaced topographic features formed over a substrate; and

the spacer material layer formed over the substrate and in direct contact with the closely spaced topographic features and in direct contact with the widely spaced topographic features, the spacer material layer having the lesser thickness portion over the narrowly spaced topographic features and a greater thickness portion over the widely spaced topographic features;

isotropically etching the greater thickness portion of the spacer material layer to provide a partially etched spacer material layer;

unmasking the lesser thickness portion of the partially etched spacer material layer; and

anisotropically etching the partially etched spacer material layer to provide a plurality of uniform linewidth spacers in direct contact with the narrowly spaced topographic features and in direct contact with the widely spaced topographic features.

10. The method of claim 9 wherein the masking is a complete masking.

11. The method of claim 9 wherein the masking is an incomplete masking.

12. The method of claim 9 wherein the substrate comprises a semiconductor substrate.

13. The method of claim 12 wherein the narrowly spaced topographic features and the widely spaced topographic features comprise gates within field effect devices.

14. A method for fabricating a microelectronic structure comprising:

anisotropically etching, while using a two-step anisotropic etch method that includes at least one masking step, a spacer material layer within a structure that includes;

a plurality of narrowly spaced topographic features and a plurality of widely spaced topographic features formed over a substrate; and

the spacer material layer formed over the substrate, the narrowly spaced topographic features and the widely spaced topographic features, the spacer material layer having the lesser thickness portion over the narrowly spaced topographic features and a greater thickness portion over the widely spaced topographic features;

the anisotropically etching using the two step anisotropic etch method includes a first anisotropic etch that provides uniform linewidth spacers adjoining the narrowly spaced topographic features while masking the widely spaced topographic features, and a second anisotropic etch that separately provides uniform linewidth spacers adjoining the widely spaced topographic features while masking the narrowly spaced topographic features.

15. The method of claim 14 wherein the first anisotropic etch is undertaken prior to the second anisotropic etch.

16. The method of claim 14 wherein the first anisotropic etch is undertaken after the second anisotropic etch.

17. The method of claim 14 wherein the two-step anisotropic etch method includes:

a first anisotropic etch that provides the uniform linewidth spacers adjoining the narrowly spaced topographic features and a partially etched spacer material layer over the widely spaced topographic features, absent masking;

a second anisotropic etch method that provides the uniform linewidth spacers adjoining the widely spaced topographic features while masking the narrowly spaced topographic features and the uniform linewidth spacers adjoining the narrowly spaced topographic features.

18. The method of claim 17 wherein the narrowly spaced topographic features and the widely spaced topographic features comprise gates within field effect transistors.