ESD network circuit with a through wafer via structure and a method of manufacture

• US 8,232,625 B2
• Filed: 03/26/2009
• Issued: 07/31/2012
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H.
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/411,612
• Publication Number:
  US 20100244187A1
• Time in Patent Office: 1,223 Days
• Field of Search: 257/213, 257/288, 257355-363, 257/618, 257/621, 257/665, 257/E21.001, 257/E21.532, 257/E21.536, 257/E21.575, 257/E21.597, 257/E23.001, 257/E23.01, 257/E23.011, 438/584, 438/597, 438/666, 438/667, 438/668
• US Class Current: 257/621
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The present invention generally relates to a circuit structure and a method of manufacturing a circuit, and more specifically to an electrostatic discharge (ESD) circuit with a through wafer via structure and a method of manufacture. An ESD structure includes an ESD active device and at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate. An apparatus includes an input, at least one power rail and an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate. A method, includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

Claims

1. An electrostatic discharge (ESD) structure, comprising:

an ESD active device; and

at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate,

wherein the at least one through wafer via structure surrounds the ESD active device to form a guard ring to prevent minority carrier migration.

2. The ESD structure of claim 1, wherein the at least one through wafer via structure comprises a conductor material or an insulator material.

3. The ESD structure of claim 1, wherein the at least one through wafer via structure is in contact with a negative power supply and a ground plane formed on a bottom of the substrate.

4. The ESD structure of claim 1, further comprising at least one inductor, wherein the at least one inductor is electrically connected to the at least one through wafer via.

5. The ESD structure of claim 1, wherein the ESD active device comprises a dual diode circuit.

6. The ESD structure of claim 1, further comprising a ground plane formed on a bottom of the substrate and electrically connected to the at least one through wafer via structure.

7. The ESD structure of claim 6, further comprising additional through wafer vias in contact with the ground plane and forming portions of the guard ring.

8. The ESD structure of claim 7, further comprising further through wafer vias in contact with the ground plane, which are structured and arranged to lower the resistance of the ESD structure at least one of laterally and vertically.

9. The ESD structure of claim 7, further comprising at least one through wafer via formed between elements of the ESD active device to prevent intra-circuit minority carrier migration between the elements of the ESD active device.

10. The ESD structure of claim 7, wherein the guard ring is structured and arranged to prevent at least one of:

injection of minority carriers into the ESD structure from one or more external sources; and

the injection of minority carriers to the one or more external sources from the ESD active device.

11. An electrostatic discharge (ESD) structure, comprising:

an ESD active device;

at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate;

at least one inductor, wherein the at least one inductor is electrically connected to the at least one through wafer via; and

an inductor shield formed between the at least one inductor and the substrate.

12. An apparatus, comprising:

an input;

at least one power rail; and

an ESD circuit electrically connected between the input and the at least one power rail,

wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate; and

at least one of the at least one through wafer via structure and at least one additional through wafer via structure is in contact with a ground plane and provides a guard ring to prevent minority carrier migration.

13. The apparatus of claim 12, further comprising at least one further through wafer via in contact with the ground plane and structured and arranged to lower the resistance of the ESD structure at least one of laterally and vertically.

14. An apparatus, comprising:

an input;

at least one power rail;

an ESD circuit electrically connected between the input and the at least one power rail,

wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate; and

the at least one through wafer via structure is in contact with a negative power supply and a ground plane formed on a bottom of the substrate.

15. An apparatus, comprising:

an input;

at least one power rail;

an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate; and

a ground plane formed on a bottom of the substrate electrically connected to the at least one through wafer via structure.

16. An apparatus, comprising:

an input;

at least one power rail; and

an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate; and

at least one inductor, wherein the at least one inductor is electrically connected to the at least one through wafer via.

17. The apparatus of claim 16, further comprising an inductor shield formed between the at least one inductor and the substrate.

18. A method, comprising:

forming an ESD active device on a substrate;

forming a ground plane on a backside of the substrate; and

forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate,

wherein the at least one through wafer via structure is structured and arranged to additionally provide a guard ring to prevent minority carrier migration.

19. The method of claim 18, further comprising forming at least one additional through wafer via in contact with the ground plane, which forms portions of the guard ring.

20. The method of claim 18, further comprising forming at least one further through wafer via in contact with the ground plane and structured and arranged to lower the resistance of the substrate at least one of laterally and vertically.

21. A method, comprising:

forming an ESD active device on a substrate;

forming a ground plane on a backside of the substrate;

forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate; and

forming at least one inductor on the substrate, wherein the at least one inductor is electrically connected to the at least one through wafer via.

22. The method of claim 21, further comprising providing an inductor shield between the at least one inductor and the substrate.