Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device

• US 8,232,627 B2
• Filed: 09/21/2009
• Issued: 07/31/2012
• Est. Priority Date: 09/21/2009
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bryant, Andres, Nowak, Edward J.
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Rodela, Eduardo A
• Application Number:
  US12/563,195
• Publication Number:
  US 20110068399A1
• Time in Patent Office: 1,044 Days
• Field of Search: 257/67, 257/288, 257/353, 257/618, 257/623, 257/E21.377, 438/39, 438/164, 438/412
• US Class Current: 257/623
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

Claims

1. A device comprising:

a semiconductor layer;

multiple gates on said semiconductor layer, said gates defining channel regions in said semiconductor layer for multiple planar field effect transistors connected in a series;

gate sidewall spacers adjacent to said gates;

source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; and

a conformal conductive layer above said multiple planar field effect transistors, said conformal conductive layer conformally covering said source/drain regions, said gate sidewall spacers and said gates, being electrically isolated from said gates, and being in contact with said source/drain regions,

said conformal conductive layer comprising a conductive material having a higher resistance than said channel regions when said multiple planar field effect transistors are in an “

on”

state and a lower resistance than said channel regions when said multiple planar field effect transistors are in an “

off”

state.

2. The device of claim 1, said conformal conductive layer comprising any one of a polysilicon layer doped with a same type dopant as said source/drain regions and a metal layer.

3. The device of claim 1, further comprising, for each gate,

a dielectric cap layer on a top surface of said gate;

and

dielectric spacers positioned laterally immediately adjacent to said gate, said dielectric cap layer and said dielectric spacers electrically isolating said gate from said conformal conductive layer.

5. The device of claim 1, further comprising:

a first via electrically connecting both said conformal conductive layer and a first source/drain region of a first field effect transistor in said series to a first supply voltage; and

a second via electrically connecting both said conformal conductive layer and a last source/drain region of a last field effect transistor in said series to a second supply voltage different from said first supply voltage.

4. A device comprising:

a semiconductor layer;

multiple gates on said semiconductor layer, said gates defining channel regions in said semiconductor layer for multiple planar field effect transistors connected in a series;

gate sidewall spacers adjacent to said gates;

source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor;

a conformal conductive layer above said multiple planar field effect transistors, said conformal conductive layer conformally covering said source/drain regions, said gate sidewall spacers and said gates, being electrically isolated from said gates, and being in contact with said source/drain regions; and

a conformal dielectric layer electrically isolating said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor layer and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor layer.

6. A device comprising:

an isolation layer;

a semiconductor fin on said isolation layer;

multiple gates on said semiconductor fin, said gates defining channel regions in said semiconductor fin for multiple non-planar field effect transistors connected in a series;

gate sidewall spacers adjacent to said gates;

source/drain regions within said semiconductor fin on opposing sides of each of said channel regions such that each portion of said semiconductor fin between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; and

a conformal conductive layer over said multiple non-planar field effect transistors, said conformal conductive layer conformally covering said source/drain regions, said gate sidewall spacers and said gates, being electrically isolated from said gates, and being in contact with said source/drain regions,

said conformal conductive layer comprising a conductive material having a higher resistance than said channel regions when said multiple non-planar field effect transistors are in an “

on”

state and a lower resistance than said channel regions when said multiple non-planar field effect transistors are in an “

off”

state.

7. The device of claim 6, said conformal conductive layer comprising any one of a polysilicon layer doped with a same type dopant as said source/drain regions and a metal layer.

8. The device of claim 6, said non-planar field effect transistors comprising fin-type field effect transistors and said device further comprising:

a dielectric cap layer on a top surface of said semiconductor fin; and

a conformal dielectric layer electrically isolating said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor fin and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor fin.

9. The device of claim 6 further comprising:

a first via electrically connecting both said conformal conductive layer and a first source/drain region of a first field effect transistor in said series to a first supply voltage; and

a second via electrically connecting both said conformal conductive layer and a last source/drain region of a last field effect transistor in said series to a second supply voltage different from said first supply voltage.

10. A device comprising:

an isolation layer;

a semiconductor fin on said isolation layer;

multiple gates on said semiconductor fin, said gates defining channel regions in said semiconductor fin for multiple non-planar field effect transistors connected in a series;

gate sidewall spacers adjacent to said gates;

source/drain regions within said semiconductor fin on opposing sides of each of said channel regions such that each portion of said semiconductor fin between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor;

a conformal conductive layer over said multiple non-planar field effect transistors, said conformal conductive layer conformally covering said source/drain regions, said gate sidewall spacers and said gates, being electrically isolated from said gates, and being in contact with said source/drain regions; and

a non-planar field effect transistors comprising tri-gate field effect transistors and said device further comprising a conformal dielectric layer over said gates so as to electrically isolate said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor fin and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor fin.

11. A device comprising:

a semiconductor layer;

multiple gates on said semiconductor layer, said gates defining channel regions in said semiconductor layer for multiple planar field effect transistors connected in a series;

source/drain regions within said semiconductor layer on opposing sides of each of said channel regions such that each portion of said semiconductor layer between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; and

a conformal conductive layer above said multiple planar field effect transistors, electrically isolated from said gates, and in contact with said source/drain regions, said conformal conductive layer comprising a conductive material having a higher resistance than said channel regions when said multiple planar field effect transistors are in an “

on”

state and a lower resistance than said channel regions when said multiple planar field effect transistors are in an “

off”

state.

12. The device of claim 11, said conformal conductive layer comprising any one of a polysilicon layer doped with a same type dopant as said source/drain regions and a metal layer.

13. The device of claim 11, further comprising, for each gate,

a dielectric cap layer on a top surface of said gate;

and

dielectric spacers positioned laterally immediately adjacent to said gate, said dielectric cap layer and said dielectric spacers electrically isolating said gate from said conformal conductive layer.

14. The device of claim 11, further comprising a conformal dielectric layer electrically isolating said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor layer and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor layer.

15. The device of claim 11, further comprising:

a first via electrically connecting both said conformal conductive layer and a first source/drain region of a first field effect transistor in said series to a first supply voltage; and

a second via electrically connecting both said conformal conductive layer and a last source/drain region of a last field effect transistor in said series to a second supply voltage different from said first supply voltage.

16. A device comprising:

an isolation layer;

a semiconductor fin on said isolation layer;

multiple gates on said semiconductor fin, said gates defining channel regions in said semiconductor fin for multiple non-planar field effect transistors connected in a series;

source/drain regions within said semiconductor fin on opposing sides of each of said channel regions such that each portion of said semiconductor fin between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor; and

a conformal conductive layer over said multiple non-planar field effect transistors, electrically isolated from said gates, and in contact with said source/drain regions, said conformal conductive layer comprising a conductive material having a higher resistance than said channel regions when said multiple non-planar field effect transistors are in an “

on”

state and a lower resistance than said channel regions when said multiple non-planar field effect transistors are in an “

off”

state.

17. The device of claim 16, said conformal conductive layer comprising any one of a polysilicon layer doped with a same type dopant as said source/drain regions and a metal layer.

18. The device of claim 16, said non-planar field effect transistors comprising fin-type field effect transistors and said device further comprising:

a dielectric cap layer on a top surface of said semiconductor fin; and

a conformal dielectric layer electrically isolating said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor fin and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor fin.

19. The device of claim 16, said non-planar field effect transistors comprising tri-gate field effect transistors and said device further comprising a conformal dielectric layer over said gates so as to electrically isolate said gates from said conformal conductive layer, said conformal dielectric layer having, at opposing ends of said semiconductor fin and between any adjacent gates, openings through which said conformal conductive layer contacts said semiconductor fin.

20. The device of claim 16, further comprising:

a first via electrically connecting both said conformal conductive layer and a first source/drain region of a first field effect transistor in said series to a first supply voltage; and

a second via electrically connecting both said conformal conductive layer and a last source/drain region of a last field effect transistor in said series to a second supply voltage different from said first supply voltage.