Reliability enhancement of metal thermal interface

• US 8,232,636 B2
• Filed: 01/26/2010
• Issued: 07/31/2012
• Est. Priority Date: 01/26/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Iruvanti, Sushumna, Langlois, Richard, Liu, Hsichang, Zheng, Jiantao, Humenik, James N, Natarajan, Govindarajan, Sikka, Kamal K, Toy, Hilton T, Monjeau, Gregg B, Kapfhammer, Mark
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US12/693,646
• Publication Number:
  US 20110180923A1
• Time in Patent Office: 917 Days
• Field of Search: 257/706, 257/707, 257/704, 257/782, 257/783, 438/118, 438/122, 438/125
• US Class Current: 257/707
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Claims

1. A method of forming an electronic package, comprising:

providing a chip having a frontside and a backside;

providing a chip carrier having a top surface and a bottom surface;

bonding the frontside of the chip to the top surface of the chip carrier;

dispensing a seal material at a periphery of the top surface of the chip carrier;

providing a lid;

providing a solder TIM having a first side and a second side, wherein the first side of the TIM contacts the backside of the chip and the second-side of the TIM contacts the lid;

performing a reflow to melt the TIM, wherein the first side of the TIM is bonded to the backside of the chip and the second side of the TIM is bonded to the lid;

curing the seal material, wherein the lid is attached to the top surface of the chip carrier;

injecting backfill material into a space between the top surface of the chip carrier and the lid, wherein the backfill material abuts sides of the TIM and fills the space; and

curing the backfill material.

2. The method according to claim 1, wherein the injecting step comprises injecting the backfill material through fill and vent holes in the lid.

3. The method according to claim 1, wherein the injecting step comprises injecting the backfill material through a gap in the seal material.

4. The method according to claim 1, wherein the lid includes a pedestal and the second side of the TIM is bonded to the pedestal.

5. The method according to claim 1, wherein the chip carrier is an organic laminate.

6. The method according to claim 1, wherein the chip carrier is a multi-layer ceramic substrate.

7. The method according to claim 1, wherein the seal is selected from the group consisting of:

silicone elastomer adhesive, epoxy adhesive, modified epoxy and modified silicone adhesive.

8. The method according to claim 1, wherein the backfill material is a resin.

9. The method according to claim 1, wherein the TIM is In.

10. A method of forming an electronic package, comprising:

providing a chip having a frontside and a backside;

providing a chip carrier having a top surface and a bottom surface;

bonding the frontside of the chip to the top surface of the chip carrier;

dispensing a seal material at a periphery of the top surface of the chip carrier;

providing a lid having at least one fill hole and at least one vent hole;

providing a TIM having a first side and a second side, wherein the first side of the TIM contacts the backside of the chip and the second side of the TIM contacts the lid;

performing a solder reflow to melt the TIM, wherein the first side of the TIM is bonded to the chip and the second side of the TIM is bonded to the lid;

injecting backfill material through the fill hole and the vent hole, wherein the backfill material abuts sides of the TIM and fills a cavity between the chip carrier and the lid; and

curing the seal material and the backfill material simultaneously, wherein the lid is bonded to the top surface of the chip carrier.

11. The method according to claim 10, wherein the backfill material is selected from the group consisting of:

epoxy, modified epoxy, modified silicone or a polyimide.

12. The method according to claim 11, wherein the backfill material has a modulus in the range from about 1 GPa to 20 GPa.

13. The method according to claim 10, wherein the TIM is selected from the group consisting of:

In, In—

Ag alloy, In—

Sn alloy, Bi and its alloys, Sn—

Ag—

Cu (SAC) lead-free solder and high thermal conductivity material.

14. The method according to claim 13, wherein the TIM has a thickness from about 1 mil to 20 mil.

15. An electronic package, comprising:

a chip having a frontside and a backside;

a chip carrier having a top surface and a bottom surface, wherein the frontside of the chip is bonded to the top surface of the chip carrier;

a lid;

a TIM having a first side and a second side, wherein the first side of the TIM is in contact with the backside of the chip, the second side of the TIM is bonded to the lid and the lid is attached to the top surface of the chip carrier at a periphery with a seal; and

backfill material in a space between the top surface of the chip carrier and the lid, wherein the backfill material abuts sides of the TIM, wherein the backside of the chip includes a Cr/Ni/Au multilayer stack.

16. The electronic package according to claim 15, wherein the lid includes at least one fill hole.

17. The electronic package according to claim 15, wherein the multilayer stack is Ti/NiV/Au.

18. The electronic package according to claim 16, wherein the lid also includes at least one vent hole.

19. The electronic package according to claim 18, wherein the fill hole and the vent hole are diagonally across from each other.

20. The electronic package according to claim 18, wherein the fill hole and the vent hole are adjacent to each other.

21. The electronic package according to claim 18, wherein the fill hole and the vent hole are on opposite sides.

22. The electronic package according to claim 15, wherein the backfill material is a resin.

23. The electronic package according to claim 15, wherein the backfill material is selected from the group consisting of:

epoxy, modified epoxy, silicone and modified silicone.

24. The electronic package according to claim 23, wherein the backfill material has a modulus in the range from about 1 GPa to 20 GPa.