Liquid crystal display device with light-shielding color filter pattern and method for fabricating the same

• US 8,233,120 B2
• Filed: 01/04/2012
• Issued: 07/31/2012
• Est. Priority Date: 12/26/2002
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Woong-Kwon, Park, Seung-Ryull
• Primary Examiner(s): Nguyen, Hoan C
• Application Number:
  US13/343,351
• Publication Number:
  US 20120099059A1
• Time in Patent Office: 209 Days
• Field of Search: 349/106, 345/88
• US Class Current: 349/106
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A liquid crystal display device includes gate and data lines defining a pixel region on a first substrate. A first insulating layer covers the gate line and a gate electrode. A thin film transistor, formed at a crossing region of the gate and data lines, has the gate electrode, a semiconductor layer, a source electrode, and a drain electrode. A red, green or blue color filter is formed over the first insulating layer in the pixel region. A drain contact hole exposes the drain electrode. A light-shielding color filter pattern including at least two of red, green and blue resins is formed over the semiconductor layer. A pixel electrode is formed over the color filter in the pixel region and contacts the drain electrode. A common electrode is formed on a second substrate facing the first substrate with a liquid crystal layer interposed between the common and pixel electrodes.

Claims

1. An array substrate for a liquid crystal display device, comprising:

a plurality of gate lines formed on a first substrate along a transverse direction, each gate line including a gate electrode;

a first insulating layer formed on the first substrate to cover the gate lines and the gate electrodes;

a plurality of data lines formed on the first insulating layer along a longitudinal direction, the data lines defining a plurality of pixel regions with the gate lines and each including a source electrode;

a thin film transistor formed at a crossing region of each of the gate and data lines, each thin film transistor including one of the gate electrodes, a semiconductor layer, one of the source electrodes, and a drain electrode;

a color filter over the first insulating layer in each pixel region, each color filter having one of red, green or blue colors, the color filters having a plurality of drain contact holes exposing the drain electrodes;

a light-shielding color filter pattern over each thin film transistor, each light-shielding color filter pattern including red, green and blue color filter patterns, wherein a first color filter pattern of red, green and blue color filter patterns has a trench accommodating a second color filter pattern of the red, green and blue color filter patterns; and

a pixel electrode over the color filter in each pixel region, each pixel electrode contacting one of the drain electrodes.

2. The array substrate according to claim 1, wherein the trench corresponding to the semiconductor layer.

3. The array substrate according to claim 1, wherein the drain electrode is spaced apart from the source electrode such that a portion of the semiconductor layer is exposed through a space between the source electrode and the drain electrode.

4. The array substrate according to claim 3, wherein the trench corresponds to the portion of the semiconductor layer.

5. The array substrate according to claim 1, wherein a third color filter pattern of red, green and blue color filter patterns is stacked on the second color filter pattern.

6. The array substrate according to claim 1, further comprising a second insulating layer between the thin film transistors and the light-shielding color filter patterns and between the first insulating layer and the color filters, wherein the second insulating layer covers the source electrodes, the drain electrodes and the data lines and wherein the drain contact holes extend through the second insulating layer.

7. The array substrate according to claim 1, further comprising a third insulating layer between the color filters and the pixel electrodes, wherein the third insulating layer covers the color filters and the light-shielding color filter patterns.

8. The array substrate according to claim 1, wherein a portion of each gate line acts as a first capacitor electrode, wherein the liquid crystal display device further comprises a second capacitor electrode on the first insulating layer over each portion of the gate line, wherein the second capacitor electrode and the portion of the gate line constitute a storage capacitor with the first insulating layer interposed between the portion of the gate line and the second capacitor electrode, wherein each color filter includes a capacitor contact hole exposing the second capacitor electrode, and wherein the pixel electrodes contact the second capacitor electrodes through the capacitor contact holes.

9. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a plurality of gate lines on a first substrate along a transverse direction, each gate line including a gate electrode;

forming a first insulating layer on the first substrate to cover the gate lines and the gate electrodes;

forming a plurality of data lines on the first insulating layer along a longitudinal direction, the data lines defining a plurality of pixel regions with the gate lines and each including a source electrode;

forming a thin film transistor formed at a crossing region of each of the gate and data lines, each thin film transistor including one of the gate electrodes, a semiconductor layer, one of the source electrodes, and a drain electrode;

forming a color filter over the first insulating layer in each pixel region and a light-shielding color filter pattern over each thin film transistor, each color filter having one of red, green or blue colors, each light-shielding color filter pattern including red, green and blue color filter patterns, wherein a first color filter pattern of red, green and blue color filter patterns has a trench accommodating a second color filter pattern of the red, green and blue color filter patterns; and

forming a pixel electrode over the color filter in each pixel region, each pixel electrode contacting one of the drain electrodes.

10. The method according to claim 9, wherein the trench corresponding to the semiconductor layer.

11. The method according to claim 9, wherein the drain electrode is spaced apart from the source electrode such that a portion of the semiconductor layer is exposed through a space between the source electrode and the drain electrode.

12. The method according to claim 11, wherein the trench corresponds to the portion of the semiconductor layer.

13. The method according to claim 9, wherein a third color filter pattern of red, green and blue color filter patterns is stacked on the second color filter pattern.

14. The method according to claim 9, further comprising forming a second insulating layer between the thin film transistors and the light-shielding color filter patterns and between the first insulating layer and the color filters, wherein the second insulating layer covers the source electrodes, the drain electrodes and the data lines and wherein the drain contact holes extend through the second insulating layer.

15. The method according to claim 9, further comprising forming a third insulating layer between the color filters and the pixel electrodes, wherein the third insulating layer covers the color filters and the light-shielding color filter patterns.

16. The method according to claim 9, wherein the step of forming the plurality of data lines includes forming a first capacitor electrode on the first insulating layer over a portion of each gate line, the portion of the gate line acts as a second capacitor electrode, wherein the first capacitor electrode and the portion of the gate line constitute a storage capacitor with the first insulating layer interposed between the portion of the gate line and the first capacitor electrode, wherein each color filter includes a capacitor contact hole exposing the first capacitor electrode, and wherein the pixel electrodes contact the first capacitor electrodes through the capacitor contact holes.