Computer system including peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits

• US 8,234,436 B2
• Filed: 04/15/2011
• Issued: 07/31/2012
• Est. Priority Date: 05/14/1999
• Status: Expired due to Term

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis LLC (Acqis Technology, Inc.)
• Inventors: Chu, William W. Y.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/087,912
• Publication Number:
  US 20110208893A1
• Time in Patent Office: 473 Days
• Field of Search: 710104-119, 710 62- 64, 710 72- 74, 710 8- 19, 710300-317
• US Class Current: 710/313
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Claims

1. A modular computer system comprising:

a modular computer comprising

a connector configured to couple to a console;

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

an integrated central processing unit and graphics controller configured as a single chip, the integrated central processing unit and graphics controller comprising an interface directly coupled to the first LVDS channel to communicate encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form over the first LVDS channel; and

a system memory directly coupled to the integrated central processing unit and graphics controller,

wherein the connector is configured to convey the encoded address and data bits of PCI bus transaction in serial form to the console upon coupling the connector to the console.

2. The modular computer system of claim 1, further comprising a second LVDS channel coupled to the integrated central processing unit and graphics controller to convey digital video data.

3. The modular computer system of claim 1, further comprising the console, and the console comprises an interface controller that is configured to couple to the connector for communication of the encoded address and data bits of PCI bus transaction in serial form.

4. The modular computer system of claim 2, wherein the connector is coupled to the integrated central processing unit and graphics controller through the second LVDS channel, and the connector is configured to convey the digital video data to the console upon coupling the connector to the console.

5. The modular computer system of claim 4, further comprising the console, the console comprises a LCD display, and the console is configured to receive the digital video data from the integrated central processing unit and graphics controller through the second LVDS channel and the connector.

6. The modular computer system of claim 3, wherein the console comprises a mass storage device coupled to the interface controller.

7. A modular computer system comprising:

a modular computer comprising

a connector configured to couple to a console;

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

an integrated central processing unit and graphics controller configured as a single chip;

a peripheral bridge directly coupled to the integrated central processing unit and graphics controller without any intervening Peripheral Component Interconnect (PCI) bus, the peripheral bridge directly coupled to the first LVDS channel to communicate encoded address and data bits of PCI bus transaction in serial form over the first LVDS channel; and

a system memory directly coupled to the integrated central processing unit and graphics controller,

wherein the connector is configured to convey the encoded address and data bits of PCI bus transaction in serial form to the console upon coupling the connector to the console.

8. The modular computer system of claim 7, further comprising a second LVDS channel coupled to the integrated central processing unit and graphics controller to convey digital video data.

9. The modular computer system of claim 7, further comprising the console, and the console comprises an interface controller that is configured to couple to the connector for communication of the encoded address and data bits of PCI bus transaction in serial form.

10. The modular computer system of claim 8, wherein the connector is coupled to the integrated central processing unit and graphics controller through the second LVDS channel, and the connector is configured to convey the digital video data to the console upon coupling the connector to the console.

11. The modular computer system of claim 10, further comprising the console, the console comprises a LCD display, and the console is configured to receive the digital video data from the integrated central processing unit and graphics controller through the second LVDS channel and the connector.

12. The modular computer system of claim 9, wherein the console comprises a mass storage device coupled to the interface controller.

13. A computer system comprising:

a first low voltage differential signal (LVDS) channel comprising at least two sets of unidirectional, multiple serial bit channels to convey data in opposite directions;

a central processing unit comprising a peripheral controller integrated with the central processing unit as a single chip, the peripheral controller directly coupled to the first LVDS channel to communicate encoded address and data bits of Peripheral Component Interconnect (PCI) bus transaction in serial form over the first LVDS channel;

a system memory directly coupled to the central processing unit; and

a mass storage device coupled to the central processing unit;

wherein the central processing unit comprises a graphics controller integrated in the single chip, and further comprising a second LVDS channel directly coupled to the graphics controller in the single chip to convey digital video data.

14. The computer system of claim 13, further comprising an enclosure with a connector, and the connector is coupled to the first LVDS channel to convey the encoded address and data bits of PCI bus transaction in LVDS form.