Systems and method for data survivability

• US 8,234,461 B2
• Filed: 03/31/2009
• Issued: 07/31/2012
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Steffler, Joseph Bernard
• Primary Examiner(s): Dickson, Paul N
• Assistant Examiner(s): Verley, Nicole
• Application Number:
  US12/415,019
• Publication Number:
  US 20100250057A1
• Time in Patent Office: 1,218 Days
• Field of Search: 711/5, 711/100, 711/117, 711/148, 714/48, 714/798
• US Class Current: 711/148
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2071 using a plurality of controllers

Abstract

Systems and a method for storing data are provided. The protected memory system includes a memory array including a plurality of memory modules each separately located with respect to each other and a memory controller configured to receive data to be stored from the data acquisition unit, store the received data in corresponding memory locations in each of the plurality of memory modules wherein the stored data including error checking information, read data from a first one of the plurality of memory modules until a data error is detected at a first memory location, read data from a second memory location of a second one of the plurality of memory modules wherein the data read from the second memory location corresponds to the data read from the first memory location, and replace the data read from the first memory location with the data read from the second memory location.

Claims

1. A protected memory system for storing data for recovery after an off-normal event, said system comprising:

a memory array comprising a plurality of memory modules each separately located with respect to each other;

a memory controller communicatively coupled to a data acquisition unit and to each of the plurality of memory modules, said controller configured to;

receive data to be stored from said data acquisition unit;

store the received data in corresponding memory locations in each of the plurality of memory modules, the stored data including error checking information;

read data from a first one of the plurality of memory modules until a data error is detected at a first memory location;

read data from a second memory location of a second one of the plurality of memory modules wherein the data read from the second memory location corresponds to the data read from the first memory location; and

replace the data read from the first memory location with the data read from the second memory location.

2. A protected memory system in accordance with claim 1 wherein the data stored in one memory module of the plurality of memory modules is redundant of the received data stored in any of the others of the plurality of memory modules.

3. A protected memory system in accordance with claim 1 wherein said plurality of memory modules are separated a predetermined distance apart in a single enclosure.

4. A protected memory system in accordance with claim 3 wherein said single enclosure comprises a crash-protected enclosure.

5. A protected memory system in accordance with claim 1 wherein the first memory location from the first one of the plurality of memory modules has the same address as the second memory location in the second one of the plurality of memory modules.

6. A protected memory system in accordance with claim 1 wherein said controller is configured to output

read data from a third memory location in subsequent ones of said plurality of memory modules that correspond to the first memory location until data read from the third memory location is error-free;

and

replace the data read from the first memory location with the data read from the third memory location.

7. A protected memory system in accordance with claim 1 wherein the off-normal event comprises at least one of a high temperature event, a shock event, and a moisture event.

8. A protected memory system in accordance with claim 1 wherein said controller is configured to output only data that is error-free.

9. A protected memory system in accordance with claim 1 wherein said controller is configured to store data in said first of said plurality of memory modules that is a mirror-image of the stored data in each other of said plurality of memory modules.