Manufacturing method of semiconductor device

• US 8,236,627 B2
• Filed: 08/30/2010
• Issued: 08/07/2012
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tsubuku, Masashi, Yoshitomi, Shuhei, Tuji, Takahiro, Hosoba, Miyuki, Sakata, Junichiro, Tomatsu, Hiroyuki, Hayakawa, Masahiko
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US12/871,122
• Publication Number:
  US 20110059575A1
• Time in Patent Office: 708 Days
• Field of Search: 438/142, 438/149, 438/151
• US Class Current: 438/149
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

Claims

1. A manufacturing method of a semiconductor device comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

performing a first heat treatment on the oxide semiconductor layer after forming the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

forming a protective insulating layer on the oxide semiconductor layer; and

performing a second heat treatment in which increase and decrease in temperature are repeated plural times on the oxide semiconductor layer, after forming the protective insulating layer,

wherein a temperature of the second heat treatment is lower than a temperature of the first heat treatment.

2. The manufacturing method of a semiconductor device according to claim 1,

wherein the temperature of the second heat treatment is decreased to room temperature after the increase in temperature in the second heat treatment.

3. The manufacturing method of a semiconductor device according to claim 1,

wherein the increase and decrease in temperature are repeated 3 times to 50 times in the second heat treatment.

4. The manufacturing method of a semiconductor device according to claim 1,

wherein the second heat treatment includes a high temperature maintenance period between the increase and the decrease in temperature and includes a low temperature maintenance period between the decrease and the increase in temperature, and

wherein lengths of time of the high temperature maintenance period and the low temperature maintenance period are each more than or equal to 1 minute and less than or equal to 60 minutes.

5. The manufacturing method of a semiconductor device according to claim 1,

wherein a channel length of the oxide semiconductor layer is 20 μ

m or less.

6. The manufacturing method of a semiconductor device according to claim 1,

wherein the first heat treatment is performed in a nitrogen atmosphere or a rare gas atmosphere.

7. The manufacturing method of a semiconductor device according to claim 1,

wherein the temperature of the first heat treatment is higher than or equal to 350°

C. and lower than or equal to 750°

C.

8. The manufacturing method of a semiconductor device according to claim 1,

wherein the second heat treatment is performed in an air atmosphere, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere.

9. The manufacturing method of a semiconductor device according to claim 1,

wherein the temperature of the second heat treatment is higher than or equal to 100°

C. and lower than or equal to 300°

C.

10. A manufacturing method of a semiconductor device comprising the steps of:

forming a gate electrode layer over a substrate having an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

performing a first heat treatment on the oxide semiconductor layer after forming the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

forming a protective insulating layer on the oxide semiconductor layer; and

performing a second heat treatment on the oxide semiconductor layer, after forming the protective insulating layer,

wherein a treatment time of the second heat treatment is longer than a treatment time of the first heat treatment, and

wherein a temperature of the second heat treatment is lower than a temperature of the first heat treatment.

11. The manufacturing method of a semiconductor device according to claim 10,

wherein the treatment time of the second heat treatment is more than or equal to 1 hour and less than or equal to 50 hours.

12. The manufacturing method of a semiconductor device according to claim 10,

wherein a channel length of the oxide semiconductor layer is 20 μ

m or less.

13. The manufacturing method of a semiconductor device according to claim 10,

wherein the first heat treatment is performed in a nitrogen atmosphere or a rare gas atmosphere.

14. The manufacturing method of a semiconductor device according to claim 10,

wherein the temperature of the first heat treatment is higher than or equal to 350°

C. and lower than or equal to 750°

C.

15. The manufacturing method of a semiconductor device according to claim 10,

wherein the second heat treatment is performed in an air atmosphere, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere.

16. The manufacturing method of a semiconductor device according to claim 10,

wherein the temperature of the second heat treatment is higher than or equal to 100°

C. and lower than or equal to 300°

C.