Shielded gate trench MOSFET device and fabrication

• US 8,236,651 B2
• Filed: 08/14/2009
• Issued: 08/07/2012
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Lee, Il Kwan, Chang, Hong, Li, Wenjun, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US12/583,192
• Publication Number:
  US 20110039383A1
• Time in Patent Office: 1,089 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a plurality of trenches, including applying a first mask, wherein at least one of the plurality of trenches is formed into one or more active cell trenches, and at least one of the plurality of trenches is formed into one or more termination trenches;

forming a first polysilicon region in the one or more active cell trenches and in the one or more termination trenches;

forming an inter-polysilicon dielectric region and a termination protection region, including applying a second mask;

forming a second polysilicon region in the one or more active cell trenches and in the one or more termination trenches;

forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask;

disposing a metal layer; and

forming a source metal region and a gate metal region, including applying a fourth mask.

2. The method of claim 1, further comprising forming asymmetric sidewalls in the termination trench.

3. The method of claim 2, wherein forming asymmetric sidewalls includes etching a portion of an oxide layer that is at least in part covered due to application of the second mask.

4. The method of claim 2, wherein the asymmetric sidewalls includes a first sidewall and a second sidewall, and the first sidewall has a thicker oxide layer than the second sidewall.

5. The method of claim 1, wherein during formation of the inter-polysilicon dielectric region and the termination protection region, the second mask covers the termination trench.

6. The method of claim 1, wherein

the termination trench is wider than the active cell trench.

7. The method of claim 1, wherein the second polysilicon region included in the termination trench functions as a gate runner that is electrically connected with a gate.

8. The method of claim 1, wherein at least one of the termination trenches is formed into a gate runner trench that is electrically connected with the second polysilicon region.

9. The method of claim 1, wherein at least one of the plurality of trenches is a gate contact trench.

10. The method of claim 9, wherein the gate contact trench includes an oxide layer that lines a trench wall of the gate contact trench, and the oxide layer in a top region of the gate contact trench has a greater thickness than the oxide layer in a bottom region of the gate contact trench.

11. The method of claim 1, wherein at least one of the plurality of trenches is formed into a source polysilicon contact trench.

12. The method of claim 11, further comprising forming a source polysilicon contact opening that extends from top of the source polysilicon contact trench to substantially below midsection of the source polysilicon contact trench.

13. The method of claim 1, wherein forming the plurality of trenches includes forming a plurality of trench openings.

14. The method of claim 13, further comprising forming a plurality of spacers around the plurality of trench openings.

15. The method of claim 14, further comprising etching the plurality of trench openings.

16. The method of claim 15, wherein the plurality of trench openings are etched in a self-aligned manner.

17. The method of claim 15, further comprising, following formation of the second polysilicon region, removing the spacers.

18. The method of claim 17, further comprising implanting body material;

wherein the termination protection region protects a termination region from the body material.