×

Shielded gate trench MOSFET device and fabrication

  • US 8,236,651 B2
  • Filed: 08/14/2009
  • Issued: 08/07/2012
  • Est. Priority Date: 08/14/2009
  • Status: Active Grant
First Claim
Patent Images

1. A method for fabricating a semiconductor device, comprising:

  • forming a plurality of trenches, including applying a first mask, wherein at least one of the plurality of trenches is formed into one or more active cell trenches, and at least one of the plurality of trenches is formed into one or more termination trenches;

    forming a first polysilicon region in the one or more active cell trenches and in the one or more termination trenches;

    forming an inter-polysilicon dielectric region and a termination protection region, including applying a second mask;

    forming a second polysilicon region in the one or more active cell trenches and in the one or more termination trenches;

    forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask;

    disposing a metal layer; and

    forming a source metal region and a gate metal region, including applying a fourth mask.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×