Method and apparatus for controlling a circuit with a high voltage sense device

• US 8,236,656 B2
• Filed: 02/02/2012
• Issued: 08/07/2012
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald R.
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/365,081
• Publication Number:
  US 20120139012A1
• Time in Patent Office: 187 Days
• Field of Search: 257339-343, 257/409, 257/E29.021, 257/E29.262, 438/157, 438/282
• US Class Current: 438/282
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

A high-voltage junction field-effect transistor (JFET) includes a semiconductor substrate, a well region, first, second, and third doped regions, and first, second, and third terminals. The first doped region is disposed in the well region and the second dope region is laterally displaced from the well region. The third doped region is disposed in the well region between the first and second doped regions. A portion of the well region is substantially depleted of free charge carriers when a first voltage between the first and second terminals is greater than or equal to a pinch-off voltage. A voltage output at the third terminal is substantially proportional to the first voltage when the first voltage is less than the pinch-off voltage, and the voltage output at the third terminal is substantially fixed and less than the first voltage when the first voltage is greater than or equal to the pinch-off voltage.

Claims

1. A high-voltage junction field-effect transistor (JFET), comprising:

a semiconductor substrate having a first conductivity type;

a well region formed in the semiconductor substrate, wherein the well region has a second conductivity type;

a first doped region disposed in the well region, wherein the first doped region has the second conductivity type;

a second doped region disposed in the semiconductor substrate laterally displaced from the well region, wherein the second doped region has the first conductivity type;

a third doped region disposed in the well region laterally displaced between the first and second doped regions, wherein the third doped region has the second conductivity type;

a first terminal disposed on the first doped region to electrically couple to the well region;

a second terminal disposed on the second doped region to electrically couple to the semiconductor substrate; and

a third terminal disposed on the third doped region to electrically coupled to the well region, wherein at least a portion of the well region is configured to be substantially depleted of free charge carriers when a first voltage between the first and second terminals is greater than or equal to a pinch-off voltage, wherein a voltage output at the third terminal is substantially proportional to the first voltage when the first voltage is less than the pinch-off voltage, and wherein the voltage output at the third terminal is substantially fixed and less than the first voltage when the first voltage is greater than or equal to the pinch-off voltage.

2. The high-voltage JFET of claim 1, further comprising an oxide layer disposed on a surface of the well region between the first and third doped regions.

3. The high-voltage JFET of claim 2, wherein the oxide layer comprises a first and a second oxide layer, the high-voltage JFET further comprising a field plate disposed between the first and second oxide layers proximate to a region between the first terminal and the well region.

4. The high-voltage JFET of claim 1, wherein the first conductivity type is p-type semiconductor material and the second conductivity type is n-type semiconductor material.

5. The high-voltage JFET of claim 1, further comprising a fourth doped region embedded within the well region between the first and third doped regions, wherein the fourth doped region has the first conductivity type.

6. The high-voltage JFET of claim 5, wherein the fourth doped region is electrically coupled to the semiconductor substrate.

7. The high-voltage JFET of claim 1, wherein the second terminal is electrically coupled to a ground reference voltage of the semiconductor substrate.