Tunable spacers for improved gapfill

• US 8,236,678 B2
• Filed: 12/17/2008
• Issued: 08/07/2012
• Est. Priority Date: 12/17/2008
• Status: Expired due to Fees

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Yelehanka, Ramachandramurthy Pradeep, Mishra, Shailendra, Nagarad, Sripad
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): MCCALL SHEPARD, SONYA D
• Application Number:
  US12/336,544
• Publication Number:
  US 20100148269A1
• Time in Patent Office: 1,329 Days
• Field of Search: 438/585, 257/368, 257/E21.438, 257/E29.255
• US Class Current: 438/585
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A device that includes a substrate with an active region is disclosed. The device includes a gate disposed in the active region and tunable sidewall spacers on sidewalls of the gate. A profile of the tunable sidewall spacers includes upper and lower portions in which width of the spacers in the upper portion is reduced at a greater rate than the lower portion.

Claims

1. A method for forming a device comprising:

providing a substrate with an active region, the substrate is prepared with a gate;

forming sidewall spacers on sidewall of the gate, wherein a portion of the spacers is processed to produce an etch rate differential between the processed portion and an unprocessed portion of the spacers; and

performing a tuning process on the spacers to produce a desired profile based on the etch rate differential of the processed and unprocessed portions of the spacers.

2. The method of claim 1 wherein forming the sidewall spacers comprises:

depositing a spacer layer to cover the substrate and gate; and

patterning the spacer layer to remove horizontal components, leaving sidewall spacers on the sidewall of the gate.

3. The method of claim 1 wherein forming sidewall spacers comprises doping the sidewall spacers with etch rate controlling (ERC) dopants.

4. The method of claim 1 wherein the tuning process includes an isotropic etch.

5. The method of claim 2 wherein the sidewall spacers comprise hexochlorosilane (HCD) silicon nitride.

6. The method of claim 2 wherein the spacer layer comprises an etch rate differential between the processed portion and unprocessed portion in the tuning process.

7. The method of claim 3 wherein the ERC dopants comprise carbon.

8. The method of claim 3, wherein the ERC dopants are configured to reduce the etch rate of the spacers.

9. The method of claim 6 wherein the etch rate differential comprises an etch rate in the unprocessed portion which is higher than an etch rate in the processed portion.

10. A method for forming a device comprising:

providing a substrate with an active region, the substrate is prepared with a gate;

forming sidewall spacers on sidewall of the gate, wherein a portion of the spacers is doped with etch rate controlling (ERC) dopants to produce an etch rate differential between the doped portion and an undoped portion of the spacers in a tuning process; and

performing the tuning process on the spacers to produce a desired profile based on the etch rate differential of the doped and undoped portions of the spacers.

11. The method of claim 10 wherein:

the ERC dopants comprise carbon; and

the sidewall spacers comprise hexochlorosilane (HCD) silicon nitride.

12. A method for forming tunable sidewall spacers comprising:

providing a substrate having a feature thereon;

forming a dielectric layer on the substrate covering the feature;

patterning the dielectric layer to form sidewall spacers;

doping a portion of the sidewall spacers with etch rate controlling (ERC) dopants to produce an etch rate differential between the doped portion and an undoped portion in a tuning process; and

processing the sidewall spacers to form spacers with a desired profile based on the etch rate differential of the doped and undoped portions of the spacers.

13. The method of claim 12 wherein the dielectric layer comprises hexochlorosilane (HCD) silicon nitride.

14. The method of claim 12 wherein the dielectric layer comprises an etch rate differential between the doped portion and undoped portion in the tuning process.

15. The method of claim 12 wherein processing the sidewall spacers includes an isotropic etch.

16. The method of claim 14 wherein the etch rate differential comprises an etch rate in the undoped portion which is higher than an etch rate in the doped portion.

17. A method for forming a device comprising:

providing a substrate with an active region, the substrate is prepared with a gate;

forming sidewall spacers on sidewall of the gate, wherein a portion of the spacers is doped with etch rate controlling (ERC) dopants to produce an etch rate differential between the doped portion and an undoped portion of the spacers in a tuning process;

performing the tuning process on the spacers to produce a profile wherein a width of the spacers in the undoped portion is reduced at a greater rate than the doped portion; and

wherein the sidewall spacers comprise;

an initial width ratio before performing the tuning process on the spacers;

a final width ratio after performing the tuning process on the spacers, wherein the initial width ratio is greater than the final width ratio; and

wherein the width ratio is equaled to the width of the undoped portion of the spacers divided by the width of the doped portion of the spacers.

18. The method of claim 17, wherein the initial width ratio is greater than the final width ratio by about 0.1 to about 0.9.

19. A method for forming a device comprising:

providing a substrate with an active region, the substrate is prepared with a gate;

forming sidewall spacers on sidewall of the gate;

doping a portion of the sidewall spacers with etch rate controlling (ERC) dopants to produce an etch rate differential between the doped portion and an undoped portion of the spacers in a tuning process; and

performing the tuning process on the spacers to produce a profile wherein a width of the spacers in the undoped portion is reduced at a greater rate than the doped portion;

wherein the performing the tuning process comprises reducing the undoped portion about 50% faster than the doped portion.

20. The method of claim 19, wherein the doping a portion of the sidewall spacers comprises doping in-situ.

21. A method of forming a device which comprises:

forming a gate on a substrate;

forming a dielectric on the gate;

forming a spacer on the sidewall of the gate;

doping the spacer with dopants, wherein the dopants are configured to reduce the etch rate of the spacer; and

after forming the spacer, etching the spacer to produce a spacer profile in which a slope at an upper portion of the spacer is steeper than at a lower portion of the spacer, wherein the upper portion of the spacer is etched at a greater rate than the lower portion of the spacer.

22. The method of claim 21 wherein the etching the spacer includes an isotropic etch.

23. A method of forming a device which comprises:

forming a gate on a substrate;

forming a dielectric on the gate;

forming a spacer on the sidewall of the gate;

doping the spacer with dopants, wherein the dopants are configured to reduce the etch rate of the spacer; and

after forming the spacer, etching the spacer, wherein an upper portion of the spacer is etched at a greater rate than a lower portion of the spacer;

wherein the spacer comprises;

an initial width ratio before etching the spacer;

a final width ratio after etching the spacer, wherein the initial width ratio is greater than the final width ratio; and

wherein the width ratio is equal to, the width of the upper portion of the spacer divided by the width of the lower portion of the spacer.