Integrated package

• US 8,237,256 B2
• Filed: 02/08/2010
• Issued: 08/07/2012
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Murata Integrated Passive Solutions
• Original Assignee: IPDiA
• Inventors: Verjus, Fabrice, Yan-Nou, Jean-Marc, Chevrie, David, LeCornec, Francois, Van Veen, Nicolaas J. A.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/702,041
• Publication Number:
  US 20100308450A1
• Time in Patent Office: 911 Days
• Field of Search: 257/696, 257/737, 257/E21.506, 257/E23.023, 257/E23.169, 257/704, 438/121
• US Class Current: 257/690
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.

Claims

1. An integrated semiconductor device including:

a device substrate with a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface; and

an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring;

wherein the device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element;

the integrated semiconductor device further comprising;

electrical interconnects across the interconnection major surface; and

interconnection bumps outside the sealing ring, the interconnection bumps electrically connecting the device electrical connectors to the interconnects.

2. An integrated semiconductor device according to claim 1 further comprising at least one bonding trench around the sealing ring on the interconnect major surface for accommodating one or more of the interconnection bumps.

3. An integrated semiconductor device according to claim 1 further comprising at least one additional semiconductor device mounted on the interconnection substrate;

wherein the device substrate is connected to the at least one additional semiconductor device by the interconnects.

4. An integrated semiconductor device according to claim 1 wherein the interconnection substrate defines a device recess for holding the device substrate, wherein the sealing ring and sealing recess are provided within the device recess.

5. An integrated semiconductor device according to claim 4 further comprising an additional semiconductor device mounted on the interconnection substrate;

wherein the additional semiconductor device is mounted on the interconnection major surface and extends across the device recess.

6. An integrated semiconductor device according to claim 1 wherein the interconnection substrate is of silicon.

7. An interconnection substrate for mounting a device substrate having a device major surface, a semiconductor element on the device major surface, and device electrical connectors on the device major surface, wherein the interconnection substrate comprises:

an interconnection major surface;

electrical interconnects extending across the interconnection major surface;

at least one sealing recess recessed from the interconnection major surface;

a sealing ring surrounding the sealing recess;

bonding pads around and outside the sealing ring for connecting through interconnection bumps to the device electrical connectors on the device major surface so that the device substrate may be mounted on the interconnection substrate with the interconnection major surface facing the device major surface, with the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element.

8. An interconnection substrate according to claim 7 further comprising at least one bonding trench for accommodating one or more interconnection bumps around the sealing ring.

9. A method of mounting a device substrate having a device major surface, a semiconductor element on the device major surface, and device electrical connectors on the device major surface, the method comprising:

providing an interconnection substrate having an interconnection major surface and electrical interconnects across the interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring;

forming interconnection bumps on the electrical interconnects or the electrical connection pads;

aligning the device substrate with the interconnection substrate with the interconnection major surface facing the device major surface, with the sealing ring around the semiconductor element; and

with the interconnection bumps aligned between the device electrical connectors and the interconnects; and

bonding the device substrate to the interconnection substrate with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element and with the interconnection bumps connect the device electrical connectors and the electrical interconnects.

10. A method according to claim 9 wherein the step of providing an interconnection substrate includes:

etching the sealing recess and at least one bonding trench around the sealing recess in the interconnection major surface; and

depositing the electrical interconnect on the interconnection major surface including in the at least one bonding trench.

11. A method according to claim 9 wherein the step of bonding the device substrate to the interconnection substrate includes melting the interconnection bumps and allowing the melted interconnection bumps to solidify.