Omnibus logic element for packing or fracturing
First Claim
Patent Images
1. An integrated circuit (IC) comprising:
- a first logic element (LE) including a first lookup table (LUT); and
a second LE comprising a second LUT, a third LUT, and an adder, whereinat least one of the first LUT, the second LUT, and the third LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode;
the adder (i) receives, when the IC is configured in a ternary addition mode, a first output from the first LUT and a second output from the second LUT, and (ii) receives, when the IC is configured in a binary addition mode, the second output from the second LUT and a third output from the third LUT.
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Abstract
Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
83 Citations
19 Claims
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1. An integrated circuit (IC) comprising:
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a first logic element (LE) including a first lookup table (LUT); and a second LE comprising a second LUT, a third LUT, and an adder, wherein at least one of the first LUT, the second LUT, and the third LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode; the adder (i) receives, when the IC is configured in a ternary addition mode, a first output from the first LUT and a second output from the second LUT, and (ii) receives, when the IC is configured in a binary addition mode, the second output from the second LUT and a third output from the third LUT. - View Dependent Claims (2, 3, 4)
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5. A programmable logic device comprising:
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a plurality of logic elements arranged in an array, at least one logic element of the plurality of logic elements including (i) a fracturable lookup table (LUT) and (ii) arithmetic logic to perform arithmetic logic functions, wherein the arithmetic logic is configurable to implement a ternary adder;
wherein,the fracturable LUT is configured to enable the at least one logic element to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit (IC) comprising:
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a first logic element including a first look up table (LUT), the first LUT being configured to output a carry result from a first set of corresponding bits of at least three binary numbers; and a second logic element including a second LUT and a third LUT, the second logic element being configured to; (i) select between a first signal received from the first LUT and a second signal received from the third LUT; (ii) output a sum result from a second set of corresponding bits of the at least three binary numbers; and (iii) add the carry result and the sum result;
whereinat least one of the first LUT, the second LUT and the third LUT is configured as a fracturable LUT, operable to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification