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Omnibus logic element for packing or fracturing

  • US 8,237,465 B1
  • Filed: 03/17/2011
  • Issued: 08/07/2012
  • Est. Priority Date: 03/25/2004
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC) comprising:

  • a first logic element (LE) including a first lookup table (LUT); and

    a second LE comprising a second LUT, a third LUT, and an adder, whereinat least one of the first LUT, the second LUT, and the third LUT is configured to perform as a fracturable LUT that is configured to enable a respective LE to implement a first number of input logic functions in a first mode and a second number of input logic functions in a second mode;

    the adder (i) receives, when the IC is configured in a ternary addition mode, a first output from the first LUT and a second output from the second LUT, and (ii) receives, when the IC is configured in a binary addition mode, the second output from the second LUT and a third output from the third LUT.

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