System and method for multiple-phase clock generation

• US 8,237,485 B2
• Filed: 08/31/2010
• Issued: 08/07/2012
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Quintic Holdings (NXP Semiconductors NV)
• Inventors: Meng, Hao, Xuan, Peiqi
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Hernandez, William
• Application Number:
  US12/872,371
• Publication Number:
  US 20120007638A1
• Time in Patent Office: 707 Days
• Field of Search: 327/115, 327/117, 327/291, 327295-299
• US Class Current: 327/295
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H03K 23/50 using bi-stable regenerative trigger circuits H03K23/42 - H03K23/48 take precedence

Abstract

A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts.

Claims

1. A system for divide-by-2 clock generation comprising:

a plurality of latch pairs configured to form a loop, wherein the loop contains at least one latch pair of the plurality of latch pairs;

wherein a plurality of differential clock pairs is coupled to the plurality of latch pairs, the plurality of differential clock pairs have the same frequency, and the plurality of differential clock pairs have staggered phases;

wherein each of the plurality of differential clock pairs is coupled to one respective latch pair of the plurality of latch pairs;

wherein the loop contains all latch pairs of the plurality of latch pairs; and

wherein the plurality of the latch pairs consists of three latch pairs, and the plurality of differential clock pairs have 60-degree staggered phases.

2. A system for divide-by-2 clock generation comprising:

a plurality of latch pairs configured to form a loop, wherein the loop contains at least one latch pair of the plurality of latch pairs;

wherein a plurality of differential clock pairs is coupled to the plurality of latch pairs, the plurality of differential clock pairs have the same frequency, and the plurality of differential clock pairs have staggered phases;

wherein each of the plurality of differential clock pairs is coupled to one respective latch pair of the plurality of latch pairs; and

wherein the loop contains only one latch pair of the plurality of latch pairs, and the input of each of the remaining latch pairs of the plurality of latch pairs is coupled to the output of the only one latch pair in the loop.

3. The system of claim 2, wherein the plurality of the latch pairs consists of a first latch pair and a second latch pair, wherein the first latch pair is in the loop, the plurality of differential clock pairs consists of a 0-degree differential clock pair and a 90-degree differential clock pair, and the 0-degree differential clock pair is coupled to the first latch pair and the 90-degree differential clock pair is coupled to the second latch pair.

4. The system of claim 2, wherein the plurality of the latch pairs consists of a first latch pair, a second latch pair and a third latch pair, wherein the first latch pair is in the loop, and the plurality of differential clock pairs consists of a 0-degree differential clock pair, a 60-degree differential clock pair and a 120-degree differential clock pair, the 0-degree differential clock pair is coupled to the first latch pair, the 60-degree differential clock pair is coupled to the second latch pair, and the 120-degree differential clock pair is coupled to the third latch pair.

5. A method of generating divide-by-2 clocks, the method comprising:

providing a plurality of latch pairs;

configuring the plurality of latch pairs to form a loop wherein the loop contains at least one latch pair of the plurality of latch pairs; and

providing a plurality of differential clock pairs coupled to the plurality of latch pairs, wherein the plurality of differential clock pairs have the same frequency and the plurality of differential clock pairs have staggered phases;

wherein each of the plurality of differential clock pairs is coupled to one respective latch pair of the plurality of latch pairs;

wherein the loop contains all latch pairs of the plurality of latch pairs; and

wherein the plurality of the latch pairs consists of three latch pairs, and the plurality of differential clock pairs have 60-degree staggered phases.

6. A method of generating divide-by-2 clocks, the method comprising:

providing a plurality of latch pairs;

configuring the plurality of latch pairs to form a loop wherein the loop contains at least one latch pair of the plurality of latch pairs; and

providing a plurality of differential clock pairs coupled to the plurality of latch pairs, wherein the plurality of differential clock pairs have the same frequency and the plurality of differential clock pairs have staggered phases;

wherein each of the plurality of differential clock pairs is coupled to one respective latch pair of the plurality of latch pairs; and

wherein the loop contains only one latch pair of the plurality of latch pairs, and the input of each of the remaining latch pairs of the plurality of latch pairs is coupled to the output of the only one latch pair in the loop.

7. The method of claim 6, wherein the plurality of the latch pairs consists of a first latch pair and a second latch pair, the first latch pair is in the loop, the plurality of differential clock pairs consists of a 0-degree differential clock pair and a 90-degree differential clock pair, and the 0-degree differential clock pair is coupled to the first latch pair and the 90-degree differential clock pair is coupled to the second latch pair.

8. The method of claim 6, wherein the plurality of the latch pairs consists of a first latch pair, a second latch pair and a third latch pair, the first latch pair is in the loop, the plurality of differential clock pairs consists of a 0-degree differential clock pair, a 60-degree differential clock pair and a 120-degree differential clock pair, and the 0-degree differential clock pair is coupled to the first latch pair, the 60-degree differential clock pair is coupled to the second latch pair, and the 120-degree differential clock pair is coupled to the third latch pair.