Amplifier with integrated filter

• US 8,237,509 B2
• Filed: 09/10/2007
• Issued: 08/07/2012
• Est. Priority Date: 02/23/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Tae Wook, Klemens, Guy, Barnett, Kenneth Charles, Sangupta, Susanta, Sahota, Gurkanwal Singh
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US11/852,946
• Publication Number:
  US 20080204148A1
• Time in Patent Office: 1,793 Days
• Field of Search: 330/306, 330/124.R, 330/253
• US Class Current: 330/306
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/168 Two amplifying stages are coupled by means of a filter circuit
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45034 One or more added reactive elements, capacitive or inductive elements, to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 2203/45058 the cascode stage of the differential amplifier comprising a reactive element
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45316 the AAC comprising one or more discrete inductive elements or coils
• CPC Class Codes: H03F 2203/45396 the AAC comprising one or more switches
• CPC Class Codes: H03F 2203/7239 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0017 the device being at least one of the amplifying solid state elements of the amplifier
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3078 : Circuits generating control signals for digitally modulated signals

Abstract

An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

Claims

1. An integrated circuit comprising:

an amplifier configured to receive an input signal and provide an output signal, the amplifier comprising;

a gain stage including a transistor configured to receive the input signal at a gate and provide signal amplification for the input signal;

a filter stage stacked and coupled to the gain stage between a supply voltage and circuit ground in a common integrated circuit and configured to provide notch filtering for the input signal and generate an output signal; and

a buffer stage coupled between a load stage and the filter stage and configured to buffer a filtered signal from the filter stage.

2. The integrated circuit of claim 1, wherein the gain stage, the filter stage, and the buffer stage are stacked and coupled between a supply voltage and circuit ground.

3. The integrated circuit of claim 1, wherein the amplifier further comprises

a second filter stage coupled to the buffer stage and configured to provide additional filtering for the input signal.

4. The integrated circuit of claim 3, wherein the filter stage and the second filter stage form an elliptical lowpass filter.

5. The integrated circuit of claim 3, wherein the amplifier further comprises

a second buffer stage coupled to the second filter stage and configured to buffer a second filtered signal from the second filter stage.

6. The integrated circuit of claim 5, wherein the gain stage, the filter stage, the buffer stage, the second filter stage, and the second buffer stage are stacked and coupled between a supply voltage and circuit ground.

7. The integrated circuit of claim 1, wherein the gain stage comprises

a transistor configured to amplify the input signal and drive the filter stage.

8. The integrated circuit of claim 1, wherein the filter stage comprises

an inductor coupled to an output of the gain stage, and

a first capacitor coupled in parallel with the inductor, the inductor and the first capacitor forming a resonator tank for passing a desired signal and attenuating interfering signals near a resonant frequency of the resonator tank.

9. The integrated circuit of claim 8, wherein the filter stage further comprises

a second capacitor coupled to a first end of the inductor and forming a low impedance path at high frequencies.

10. The integrated circuit of claim 9, wherein the filter stage further comprises

a third capacitor coupled to a second end of the inductor and forming a second low impedance path at high frequencies.

11. The integrated circuit of claim 8, wherein the amplifier has a largest signal attenuation criterion at a particular frequency, and wherein the resonator tank provides a notch near the particular frequency.

12. The integrated circuit of claim 1, wherein the gain stage is configured to provide an inverting output and a non-inverting output, and wherein the filter stage comprises

a first inductor and a first capacitor coupled in parallel and to the inverting output of the gain stage, and

a second inductor and a second capacitor coupled in parallel and to the non-inverting output of the gain stage.

13. The integrated circuit of claim 12, wherein the filter stage further comprises

a third capacitor coupled between the inverting and non-inverting outputs of the gain stage.

14. The integrated circuit of claim 12, wherein the first and second inductors are formed to achieve destructive coupling.

15. The integrated circuit of claim 12, wherein the first inductor is implemented with a first spiral inductor in a clockwise direction and the second inductor is implemented with a second spiral inductor in a counter-clockwise direction.

16. The integrated circuit of claim 1, wherein the gain stage is configured to amplify a broadcast signal for Digital Video Broadcasting for Handhelds (DVB-H), Integrated Services Digital Broadcasting for Terrestrial Television Broadcasting (ISDB-T), or MediaFLO™

.

17. An apparatus comprising:

an amplifier configured to receive an input signal and provide an output signal, the amplifier comprising;

a gain stage including a transistor configured to receive the input signal at a gate and provide signal amplification for the input signal;

a filter stage stacked and coupled to the gain stage between a supply voltage and circuit ground in a common integrated circuit and configured to provide notch filtering for the input signal and generate an output signal; and

a buffer stage coupled between a load stage and the filter stage and configured to buffer a filtered signal from the filter stage.

18. The apparatus of claim 17, wherein the gain stage, the filter stage, and the buffer stage are stacked and coupled between a supply voltage and circuit ground.

19. A method comprising:

amplifying an input signal with a gain stage including a transistor configured to receive the input signal at a gate to obtain an amplified signal;

filtering the amplified signal with a filter stage stacked and coupled to the gain stage between a supply voltage and circuit ground in a common integrated circuit to generage an output signal, the gain stage and the filter stage being part of an amplifier with integrated filter; and

buffering the filtered signal with a buffer stage coupled between a load stage and the filter stage to obtain a buffered signal, the buffer stage being part of the amplifier with integrated filter.

20. An apparatus comprising:

means for amplifying an input signal with a gain stage including a transistor configured to receive the input signal at a gate to obtain an amplified signal;

means for filtering the amplified signal with a filter stage stacked and coupled to the gain stage between a supply voltage and circuit ground in a common integrated circuit to generate an output signal, the gain stage and the filter stage being part of an amplifier with integrated filter; and

means for buffering the filtered signal with a buffer stage coupled between a load stage and the filter stage to obtain a buffered signal, the means for buffering being part of the amplifier with integrated filter.