Register allocation for message sends in graphics processing pipelines
First Claim
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1. A method comprising:
- identifying live ranges of variables used in message sends for graphics processing;
modeling a plurality of physical registers and the live ranges in an interference graph;
bias coloring the interference graph based on preferred colors of the live ranges;
allocating the plurality of physical registers to the message sends based on the interference graph after bias coloring; and
identifying live ranges of variables used in message sends from shaders in a graphics pipeline.
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Abstract
Message sends may be implemented in a graphics pipeline using biased graph coloring. Registers may be allocated by shaders for message sends using biased graph coloring.
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Citations
19 Claims
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1. A method comprising:
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identifying live ranges of variables used in message sends for graphics processing; modeling a plurality of physical registers and the live ranges in an interference graph; bias coloring the interference graph based on preferred colors of the live ranges; allocating the plurality of physical registers to the message sends based on the interference graph after bias coloring; and identifying live ranges of variables used in message sends from shaders in a graphics pipeline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a plurality of registers for message sends in a graphics pipeline; and a shader to; identify live ranges of variables used in the message sends, model the plurality of physical registers and the live ranges in an interference graph, bias coloring the interference graph based on preferred colors of the live ranges, and allocate the plurality of physical registers to the message sends based on the interference graph after bias coloring. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification