3D grid controllable liquid crystal lens and manufacturing method thereof

• US 8,237,890 B2
• Filed: 10/06/2010
• Issued: 08/07/2012
• Est. Priority Date: 10/19/2009
• Status: Active Grant

• Current Assignee: Silicon Touch Technology Inc.
• Original Assignee: Silicon Touch Technology Inc.
• Inventors: Chang, Chi-Lone, Chin, Chi-Yuan
• Primary Examiner(s): Vu, Phu
• Application Number:
  US12/898,721
• Publication Number:
  US 20110090451A1
• Time in Patent Office: 671 Days
• Field of Search: 349 74- 75
• US Class Current: 349/74
• CPC Class Codes: G02B 3/0081 having one or more elements with analytic function to create variable power variable magnification in general G02B15/00
• CPC Class Codes: G02F 1/29 for the control of the position or the direction of light beams, i.e. deflection
• CPC Class Codes: G02F 1/291 Two-dimensional analogue deflection
• CPC Class Codes: G02F 1/294 Variable focal length devices

Abstract

A 3D grid controllable liquid crystal lens is provided. In the 3D grid controllable liquid crystal lens, at least two layers of a plurality of active device arrays are stacked on a first substrate, and a plurality of liquid crystal layer are respectively disposed on the active device arrays. Then, a driving voltage applied on each active device array is suitably controlled to control the orientation of the liquid crystal molecules, so as to generate a refractive index distribution similar to gradient-index lens in the 3D grid controllable liquid crystal lens. Therefore, the 3D grid controllable liquid crystal lens has a focusing function for focusing/diverging the light, similar to a convex lens or a concave lens. A method for manufacturing the 3D grid controllable liquid crystal lens is also provided.

Claims

1. A three-dimensional (3D) grid controllable liquid crystal lens, comprising:

a first substrate;

a plurality of first active device arrays disposed on the first substrate, each of the first active device arrays comprising a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

a first insulating layer disposed above the first active device arrays;

a plurality of first spacers disposed on the first substrate and supporting the first insulating layer, so as to form a first containing space between the first insulating layer and the first active device arrays;

a plurality of second active device arrays disposed on the first insulating layer, each of the second active device arrays comprising a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

a second insulating layer disposed above the second active device arrays;

a plurality of second spacers disposed on the first insulating layer and supporting the second insulating layer, so as to form a second containing space between the second insulating layer and the second active device arrays;

a plurality of third active device arrays disposed on the second insulating layer, each of the third active device arrays comprising a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

a second substrate comprising a common electrode disposed thereon and arranged opposite to the first substrate, and the common electrode is located between the second substrate and the third active device arrays;

a plurality of third spacers disposed on the second insulating layer and supporting the second substrate, so as to form a third containing space between the second substrate and the third active device arrays; and

a plurality of liquid crystal layers respectively disposed in the first containing space, the second containing space, and the third containing space.

2. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein each of the first active device arrays, the second active device arrays, and the third active device arrays further comprises a gate line and a source line, the gate line and the source line are interlaced, the gate line is electrically connected to a gate of the thin film transistor, and the source line electrically connected to a source of the thin film transistor.

3. The 3D grid controllable liquid crystal lens as claimed in claim 2, further comprising a gate controller and a source controller, wherein the gate controller is electrically connected to the gate line of the first active device arrays, the second active device arrays, and the third active device arrays, respectively, and the source controller is electrically connected to the source line of the first, the second, and the third active device arrays, respectively.

4. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein a plurality of first gate lines, second gate lines, and third gate lines and a plurality of first gate lines, second gate lines, and third source lines are disposed on the first substrate, wherein the first gate lines and the first source lines are respectively electrically connected to a gate and a source of the thin film transistors of the first active device arrays, the second gate lines and the second source lines are respectively electrically connected to a gate and a source of the thin film transistors of the second active device arrays via a first through hole, and the third gate lines and the third source lines are respectively electrically connected to a gate and a source of the thin film transistors of the third active device arrays via a second through hole.

5. The 3D grid controllable liquid crystal lens as claimed in claim 4, further comprising a gate controller and a source controller, wherein the gate controller is electrically connected to the first gate lines, the second gate lines, and third gate lines, respectively, and the source controller is electrically connected to the first gate lines, the second gate lines, and the third source lines, respectively.

6. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein each of the thin film transistors of the first active device arrays, the second active device arrays, and the third active device arrays comprises at least a gate, an active layer, a source, and a drain, the drain is physically connected to the transparent electrode, and when the gate is being driven, the source electrically connects to the drain via the active layer.

7. The 3D grid controllable liquid crystal lens as claimed in claim 6, wherein an electrode of each of the storage capacitors and the gate belong to a same film, and another electrode of each of the storage capacitors and the source or the drain belong to a same film.

8. The 3D grid controllable liquid crystal lens as claimed in claim 1, further comprising a sealant disposed in a periphery of the first substrate or the second substrate, and arranged between the first substrate and the second substrate.

9. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein the first substrate and the second substrate are transparent substrates.

10. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein a material of the first spacers and the second spacers comprises metal.

11. The 3D grid controllable liquid crystal lens as claimed in claim 1, wherein an alignment layer is disposed on the transparent electrode of the first active device arrays, an alignment layer is disposed on the transparent electrode of the second active device arrays, an alignment layer is disposed on the transparent electrode of the third active device arrays, and an alignment layer is disposed on the common electrode, so as to perform an alignment process on the liquid crystal layers.

12. A manufacturing method of a three-dimensional (3D) grid controllable liquid crystal lens, comprising:

providing a first substrate;

forming a plurality of first active device arrays on the first substrate, wherein each of the first active device arrays comprises a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

forming a first dielectric layer on the first substrate to cover the first active device arrays;

patterning the first dielectric layer to form a plurality of first through holes exposing the first substrate;

injecting a first spacer material into the first through holes, so as to form a plurality of first spacers on the first substrate;

forming a first insulating layer on the first dielectric layer, wherein the first spacers support the first insulating layer;

forming a plurality of second active device arrays on the first insulating layer, wherein each of the second active device arrays comprises a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

forming a second dielectric layer on the first insulating layer to cover the second active device arrays;

patterning the second dielectric layer to form a plurality of second through holes exposing the first insulating layer;

injecting a second spacer material into the second through holes, so as to form a plurality of second spacers on the first insulating layer;

forming a second insulating layer on the second dielectric layer, wherein the second spacers support the second insulating layer;

forming a plurality of third active device arrays on the second insulating layer, wherein each of the third active device arrays comprises a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

forming a third dielectric layer on the second insulating layer to cover the third active device arrays;

patterning the third dielectric layer to form a plurality of third through holes exposing the first insulating layer;

injecting a third spacer material into the third through holes, so as to form a plurality of third spacers on the second insulating layer;

assembling the first substrate with a second substrate;

removing the first dielectric layer, the second dielectric layer, and the third dielectric layer, so as to respectively form a first containing space between the first insulating layer and the first active device arrays, a second containing space between the second insulating layer and the second active device arrays, and a third containing space between the second substrate and the third active device arrays; and

injecting a liquid crystal material between the first substrate and the second substrate, so as to form a plurality of liquid crystal layers, wherein the liquid crystal layers are respectively disposed in the first containing space, the second containing space, and the third containing space, a common electrode is disposed on the second substrate, and the common electrode is arranged between the second substrate and the third active device arrays.

13. The manufacturing method as claimed in claim 12, wherein forming each of the first active device arrays comprises:

forming a gate and an electrode of the storage capacitor on the first substrate;

forming a gate insulating layer on the first substrate to cover the gate and the electrode of the storage capacitor;

forming an active layer on the gate insulating layer above the gate;

forming a patterned metal layer above the active layer and the electrode of the storage capacitor, so as to form a source, a drain, and another electrode disposed above the electrode of the storage capacitor;

forming a passivation layer on the first substrate to cover the source, the drain, and the other electrode of the storage capacitor, wherein the passivation layer has a plurality of openings to respectively expose a portion of the drain and the other electrode; and

forming a transparent conductive material on the passivation layer, so as to form the transparent electrode, wherein the transparent electrode is electrically connected to the drain and the other electrode of the storage capacitor via the openings, respectively.

14. The manufacturing method as claimed in claim 13, wherein while forming the gate a gate line is formed concurrently, while forming the source a source line is formed concurrently, the gate line electrically connects to the gate, the source line electrically connects to the source, and the gate line and the source line are interlaced.

15. The manufacturing method as claimed in claim 12, wherein forming each of the second active device arrays comprises:

forming a gate and an electrode of the storage capacitor on the first insulating layer;

forming a gate insulating layer on the first insulating layer to cover the gate and the electrode of the storage capacitor;

forming an active layer on the gate insulating layer above the gate;

forming a patterned metal layer above the active layer and the electrode of the storage capacitor, so as to form a source, a drain, and another electrode disposed above the electrode of the storage capacitor;

forming a passivation layer on the first insulating layer to cover the source, the drain, and the other electrode of the storage capacitor, wherein the passivation layer has a plurality of openings to respectively expose a portion of the drain and the other electrode; and

forming a transparent conductive material on the passivation layer, so as to form the transparent electrode, wherein the transparent electrode is electrically connected to the drain and the other electrode of the storage capacitor via the openings, respectively.

16. The manufacturing method as claimed in claim 15, wherein while forming the gate a gate line is formed concurrently, while forming the source a source line is formed concurrently, the gate line electrically connects to the gate, the source line electrically connects to the source, and the gate line and the source line are respectively extended to the first substrate via a portion of the first through holes.

17. The manufacturing method as claimed in claim 12, wherein forming each of the third active device arrays comprises:

forming a gate and an electrode of the storage capacitor on the second insulating layer;

forming a gate insulating layer on the second insulating layer to cover the gate and the electrode of the storage capacitor;

forming an active layer on the gate insulating layer above the gate;

forming a patterned metal layer above the active layer and the electrode of the storage capacitor, so as to form a source, a drain, and another electrode disposed above the electrode of the storage capacitor;

forming a passivation layer on the second insulating layer to cover the source, the drain, and the other electrode of the storage capacitor, wherein the passivation layer has a plurality of openings to respectively expose a portion of the drain and the other electrode; and

forming a transparent conductive material on the passivation layer, so as to form the transparent electrode, wherein the transparent electrode is electrically connected to the drain and the other electrode of the storage capacitor via the openings, respectively.

18. The manufacturing method as claimed in claim 17, wherein a gate line is formed concurrently while forming the gate, a source line is formed concurrently while forming the source, the gate line electrically connects to the gate, the source line electrically connects to the source, and the gate line and the source line are respectively extended to the first substrate via a portion of the second through holes.

19. The manufacturing method as claimed in claim 12, wherein a material of the first spacers and the second spacers comprises metal.

20. The manufacturing method as claimed in claim 12, further comprising forming a sealant in a periphery of the first substrate or the second substrate, and the sealant is arranged between the first substrate and the second substrate to assemble the first substrate with the second substrate.

21. The manufacturing method as claimed in claim 12, further comprising respectively forming an alignment layer on the transparent electrode of the first active device arrays, forming an alignment layer on the transparent electrode of the second active device arrays, forming an alignment layer on the transparent electrode of the third active device arrays, and forming an alignment layer on the common electrode, so as to perform an alignment process on the liquid crystal layers, respectively.

22. A three-dimensional (3D) grid controllable liquid crystal lens, comprising:

a first substrate;

a plurality of first active device arrays disposed on the first substrate, each of the first active device arrays comprising a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

a first insulating layer disposed above the first active device arrays;

a plurality of first spacers disposed on the first substrate and supporting the first insulating layer, so as to form a first containing space between the first insulating layer and the first active device arrays;

a plurality of second active device arrays disposed on the first insulating layer, each of the second active device arrays comprising a thin film transistor, a storage capacitor, and a transparent electrode electrically connected to the thin film transistor;

a second substrate comprising an electrode layer disposed thereon, the electrode layer arranged opposite to the first substrate, and the electrode layer is located between the second substrate and the second active device arrays;

a plurality of second spacers disposed on the first insulating layer and supporting the second substrate, so as to form a second containing space between the second substrate and the second active device arrays; and

a plurality of liquid crystal layers respectively disposed in the first containing space and the second containing space.