×

Printed wiring board and method for manufacturing same

  • US 8,238,114 B2
  • Filed: 08/08/2008
  • Issued: 08/07/2012
  • Est. Priority Date: 09/20/2007
  • Status: Active Grant
First Claim
Patent Images

1. A printed wiring board comprising:

  • a plurality of conductive layers having a plurality of conductive circuits;

    a plurality of resin insulation layers having a plurality of openings and including an uppermost resin insulation layer positioned as an outermost layer of the plurality of resin insulation layers, the uppermost resin insulation layer being formed on a second uppermost resin insulation layer;

    a plurality of via conductors formed in the plurality of openings, respectively, and connecting the plurality of conductive circuits in the plurality of conductive layers; and

    a plurality of component-loading pads comprising a copper foil and positioned to load an electronic component,wherein the resin insulation layers and the conductive layers are alternately laminated, the component-loading pads are formed on the uppermost resin insulation layer, the component-loading pads are truncated such that an area of a bottom surface touching a surface of the uppermost resin insulation layer is made larger than an area of a top surface on which to load the electronic component, the component-loading pads have side surfaces slanting from the top surface to the bottom surface, the top surface is substantially flat, the via conductors formed in the uppermost resin insulation layer each have a first surface in contact with one of the component-loading pads and a second surface which is opposite to the first surface and in contact with one of the via conductors formed in the second uppermost resin insulation layer, the via conductors formed in the uppermost resin insulation layer are truncated such that the first surface has a smaller area than the second surface, and the second surface has a dented portion to which the via conductor formed in the second uppermost resin insulation layer is connected.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×