Selective re-programming of analog memory cells

• US 8,238,157 B1
• Filed: 04/11/2010
• Issued: 08/07/2012
• Est. Priority Date: 04/12/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sommer, Naftali, Perlmutter, Uri, Winter, Shai
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US12/758,003
• Time in Patent Office: 849 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.19, 365/185.22
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset.

Claims

1. A method for data storage, comprising:

in a memory that includes multiple analog memory cells, defining an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states;

initially storing data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states;

after initially storing the data, programming a second group of the analog memory cells, which potentially cause interference to the first group; and

after programming the second group, selectively re-programming the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset,

wherein initially storing the data comprises writing respective storage values into the memory cells in the first group and verifying the written storage values using first verification thresholds, and wherein selectively re-programming the first group comprises re-writing the storage values that are associated with the partial subset, and verifying the re-written storage values using second verification thresholds, higher than the corresponding first verification thresholds.

2. The method according to claim 1, wherein programming the memory cells comprises writing respective storage values into the memory cells, and wherein defining the partial subset comprises including in the partial subset at least a non-erased programming state corresponding to a lowest range of the analog values among the non-erased memory states.

3. The method according to claim 1, wherein programming the memory cells comprises writing respective storage values into the memory cells, and wherein defining the partial subset comprises including in the partial subset at least a non-erased programming state corresponding to a highest range of the analog values among the non-erased memory states.

4. A method for data storage, comprising:

in a memory that includes multiple analog memory cells, defining an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states;

initially storing data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states;

after initially storing the data, programming a second group of the analog memory cells, which potentially cause interference to the first group;

after programming the second group, selectively re-programming the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset; and

programming the second group with dummy data responsively to detecting that programming of the second group is postponed, so as to cause re-programming of the first group.

5. The method according to claim 4, wherein detecting that the programming of the second group is postponed comprises detecting that a time that elapsed since the programming of the second group exceeds a predefined maximum value.

6. The method according to claim 4, wherein detecting that the programming of the second group is postponed comprises determining that shut-off of electrical power is imminent.

7. A method for data storage, comprising:

in a memory that includes multiple analog memory cells, defining an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states;

initially storing data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states;

after initially storing the data, programming a second group of the analog memory cells, which potentially cause interference to the first group;

after programming the second group, selectively re-programming the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset; and

upon preparing to read the data from the first group, applying a corrective action to the first group responsively to detecting that that the first group was not re-programmed.

8. The method according to claim 7, wherein applying the corrective action comprises programming the second group with dummy data, so as to cause re-programming of the first group.

9. The method according to claim 7, wherein applying the corrective action comprises sensing at least one analog value that was written into a respective analog memory cell in the first group and has become negative.

10. The method according to claim 7, wherein applying the corrective action comprises applying one or more programming pulses to at least one of the memory cells in the first group.

11. Apparatus for data storage, comprising:

a memory, which comprises multiple analog memory cells; and

circuitry, which is configured to define an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states, to initially store data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states, to program a second group of the analog memory cells, which potentially cause interference to the first group, after initially storing the data, and, after programming the second group, to selectively re-program the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset,

wherein the circuitry is configured to initially store the data by writing respective storage values into the memory cells in the first group and verifying the written storage values using first verification thresholds, and to selectively re-program the first group by re-writing the storage values that are associated with the partial subset and verifying the re-written storage values using second verification thresholds, higher than the corresponding first verification thresholds.

12. The apparatus according to claim 11, wherein the circuitry is configured to program the memory cells by writing respective storage values into the memory cells, and wherein the partial subset comprises at least a non-erased programming state corresponding to a lowest range of the analog values among the non-erased memory states.

13. The apparatus according to claim 11, wherein the circuitry is configured to program the memory cells by writing respective storage values into the memory cells, and wherein the partial subset comprises at least a non-erased programming state corresponding to a highest range of the analog values among the non-erased memory states.

14. Apparatus for data storage, comprising:

a memory, which comprises multiple analog memory cells; and

circuitry, which is configured to define an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states, to initially store data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states, to program a second group of the analog memory cells, which potentially cause interference to the first group, after initially storing the data, and, after programming the second group, to selectively re-program the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset,

wherein the circuitry is configured to program the second group with dummy data responsively to detecting that programming of the second group is postponed, so as to cause re-programming of the first group.

15. The apparatus according to claim 14, wherein the circuitry is configured to detect that the programming of the second group is postponed by detecting that a time that elapsed since the programming of the second group exceeds a predefined maximum value.

16. The apparatus according to claim 14, wherein the circuitry is configured to detect that the programming of the second group is postponed by determining that shut-off of electrical power is imminent.

17. Apparatus for data storage, comprising:

a memory, which comprises multiple analog memory cells; and

circuitry, which is configured to define an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states, to initially store data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states, to program a second group of the analog memory cells, which potentially cause interference to the first group, after initially storing the data, and, after programming the second group, to selectively re-program the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset,

wherein, upon preparing to read the data from the first group, the circuitry is configured to apply a corrective action to the first group responsively to detecting that that the first group was not re-programmed.

18. The apparatus according to claim 17, wherein the corrective action comprises programming the second group with dummy data, so as to cause re-programming of the first group.

19. The apparatus according to claim 17, wherein the corrective action comprises sensing at least one analog value that was written into a respective analog memory cell in the first group and has become negative.

20. The apparatus according to claim 17, wherein the corrective action comprises applying one or more programming pulses to at least one of the memory cells in the first group.