Using storage cells to perform computation

• US 8,238,173 B2
• Filed: 07/16/2009
• Issued: 08/07/2012
• Est. Priority Date: 07/16/2009
• Status: Active Grant

• Current Assignee: GSI Technology Incorporated
• Original Assignee: ZikBit Ltd
• Inventors: Akerib, Avidan, Agam, Oren, Ehrman, Eli, Meyassed, Moshe
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Graham, Kretelia
• Application Number:
  US12/503,916
• Publication Number:
  US 20110013442A1
• Time in Patent Office: 1,118 Days
• Field of Search: 365/189.15, 365/189.07, 365/191
• US Class Current: 365/189.15
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

Claims

1. A NOR device comprising:

a plurality of memory cells which store data; and

an activation unit to activate at least two of said memory cells in a column at time thereby to generate a NOR output of said data of said at least two memory cells, and wherein said activation unit comprises;

a multiple row decoder to activate at least one cell in each of more than one row of said memory cells at a time; and

an output unit at least to write the NOR'"'"'d output of at least one column of activated cells into said memory cells.

2. The NOR device according to claim 1 and wherein said memory cells form a memory array having at least a first portion to store said data and at least a second portion available for processing.

3. An in-memory processor comprising:

a memory array which stores data; and

an activation unit to activate at least two cells in a column of said memory array at the same time thereby to generate a Boolean function output of said data of said at least two cells, wherein said activation unit comprises;

a multiple row decoder to activate at least one cell in each of more than one row of said memory array at a time;

and an output unit at least to write the output of at least one column of said activated cells into said memory array, said output being said Boolean function of the said activated cells in each said column.

4. The processor according to claim 3 and wherein said memory array has at least a first portion to store said data and at least a second portion available for processing.

5. The processor according to claim 3 wherein said output unit comprises a selectively activatable inverter and wherein also comprising a controller to instruct said row decoder as to which cells to activate and to instruct said output unit when to activate said inverter thereby to generate said Boolean function.

6. The processor according to claim 3 and wherein said Boolean function is one of:

OR, NOR, AND and NAND.