Non-volatile memory device having temperature compensator and memory system thereof

• US 8,238,185 B2
• Filed: 10/29/2009
• Issued: 08/07/2012
• Est. Priority Date: 11/04/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seungjae, Lee, Sungsoo
• Primary Examiner(s): Nguyen, VanThu
• Application Number:
  US12/608,295
• Publication Number:
  US 20100110815A1
• Time in Patent Office: 1,013 Days
• Field of Search: 365/211.O, 365/212.X, 365/189.09 X, 365/211, 365/212, 365/189.09
• US Class Current: 365/211
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes: a voltage generator adjusting a DC voltage supplied into the semiconductor memory device according to a current temperature; and a control logic activating a temperature detection operation of the voltage generator and an adjustment operation of the DC voltage according to an operation mode, wherein the voltage generator adjusts the DC voltage according to offset information about the semiconductor memory device.

Claims

1. A semiconductor memory device comprising:

a voltage generator adjusting a DC voltage supplied into the semiconductor memory device according to a current temperature; and

a control logic activating a temperature detection operation of the voltage generator and an adjustment operation of the DC voltage according to an operation mode including at least one of program, read and erase modes;

wherein the voltage generator adjusts the DC voltage according to the operation mode and offset information about the semiconductor memory device.

2. The semiconductor memory device of claim 1, wherein the voltage generator comprises:

a temperature detector measuring the current temperature and outputting the measured current temperature as a temperature signal;

a temperature code generator converting the temperature signal into a temperature code corresponding to the operation mode;

a level code generator generating a level code so as to generate a DC voltage corresponding to the operation mode;

an adder receiving the level code and the temperature code and outputting the received level code and temperature code as an adjusted level code; and

a DC voltage generator generating a DC voltage corresponding to the adjusted level code.

3. The semiconductor memory device of claim 2, wherein the temperature code generator comprises:

an analog-digital converter converting the temperature signal into a first code of a digital format;

an encoder converting the first code into a second code; and

a code generator selecting a temperature code corresponding to the second code according to the operation mode and the offset information.

4. The semiconductor memory device of claim 3, wherein the temperature code generator further comprises a temperature code register to provide temperature codes corresponding to the operation mode, the offset information, or the second code.

5. The semiconductor memory device of claim 4, wherein the code generator searches the temperature code register to select the temperature code.

6. The semiconductor memory device of claim 1, further comprising a memory unit to store the offset information.

7. A method of controlling a semiconductor memory device, the method comprising:

receiving a command from an external;

adjusting DC voltages consumed during a plurality of operation procedures constituting an operation mode corresponding to the command with reference to a current temperature and a offset value in each device, the operation mode including at least one of program, read and erase modes; and

performing the plurality of operation procedures according to the adjusted DC voltages;

wherein the adjusting of the DC voltages comprises generating a temperature code with reference to at least one of the operation mode, the current temperature, and the temperature offset value.

8. The method of claim 7, wherein the adjusting of the DC voltages comprises:

measuring the current temperature with reference to a reference voltage and outputting a code corresponding to the measured current temperature;

generating the code as the temperature code with reference to the operation mode and the temperature offset value;

adding or subtracting the temperature code to or from a level code so as to generate a default value of the DC voltages; and

generating the DC voltages using the level code to or from which the temperature code is added or subtracted.

9. The method of claim 7, wherein the adjusting of the DC voltages is activated only during a read operation where an uncorrectable error is detected.

10. A memory system comprising:

a plurality of semiconductor memory devices; and

a memory controller controlling the plurality of semiconductor memory devices;

wherein each of the semiconductor memory devices comprises;

a temperature detector measuring a current temperature and outputting the measured current temperature as a temperature code;

a voltage generator adjusting a DC voltage supplied into the semiconductor memory device according to the temperature code; and

a control logic activating a temperature detection operation of the temperature detector and an adjustment operation of the DC voltage according to an operation mode including at least one of program, read and erase modes;

wherein the voltage generator adjusts the DC voltage by code operation with the temperature code and an offset code; and

wherein the offset code corresponds to the operation mode of the semiconductor memory device.