IC with MMW transceiver communications
First Claim
Patent Images
1. A circuit comprising:
- a processing module including;
a processing core; and
a first processing module millimeter wave (MMW) transceiver coupled to the processing core;
a second processing module MMW transceiver for processing requests from a plurality of peripheral components;
a main memory including;
memory; and
a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver using a first channel of a plurality of channels; and
a second memory MMW transceiver for processing memory requests from the plurality of peripheral components; and
the plurality of peripheral components, wherein each of the plurality of peripheral components comprises a peripheral MMW transceiver such that the peripheral MMW transceiver for each one of the plurality of peripheral components conveys the processing requests to the processing core via the second processing module MMW transceiver using a second channel of the plurality of channels and conveys the memory requests to the main memory via the second memory MMW transceiver using a third channel of the plurality of channels.
6 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit (IC) includes a processing module and main memory. The processing module includes a processing core and a first processing module millimeter wave (MMW) transceiver coupled to the processing core. The main memory includes memory and a first memory MMW transceiver coupled to the memory. At least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver.
-
Citations
20 Claims
-
1. A circuit comprising:
-
a processing module including; a processing core; and a first processing module millimeter wave (MMW) transceiver coupled to the processing core; a second processing module MMW transceiver for processing requests from a plurality of peripheral components; a main memory including; memory; and a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver using a first channel of a plurality of channels; and a second memory MMW transceiver for processing memory requests from the plurality of peripheral components; and the plurality of peripheral components, wherein each of the plurality of peripheral components comprises a peripheral MMW transceiver such that the peripheral MMW transceiver for each one of the plurality of peripheral components conveys the processing requests to the processing core via the second processing module MMW transceiver using a second channel of the plurality of channels and conveys the memory requests to the main memory via the second memory MMW transceiver using a third channel of the plurality of channels. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A circuit comprises:
-
a processing module including; a processing core; a first processing module millimeter wave (MMW) transceiver coupled to the processing core; and a second processing module MMW transceiver coupled to the processing core; a main memory including; memory; a first memory MMW transceiver coupled to the memory, wherein at least one of an instruction and data is conveyed between the processing core and the memory via the first processing module MMW transceiver and the first memory MMW transceiver using a first channel of a plurality of channels; and a second memory MMW transceiver coupled to the memory; and an access module including; a first access control module MMW transceiver coupled to the access control module; and a second access control module MMW transceiver coupled to the access control module, wherein a memory access request or a processing request is received via the first access control module MMW transceiver using a second channel of the plurality of channels, wherein the access module conveys the processing request to the processing core via the second access control module MMW transceiver and the second processing module MMW transceiver, and wherein the access module conveys the memory access request to the memory via the second access control module MMW transceiver and the second memory MMW transceiver. - View Dependent Claims (9, 10, 11, 12, 13)
-
-
14. A circuit comprises:
-
a core access control module including; a first core millimeter wave (MMW) transceiver operable to convey a memory message with a main memory via a first memory MMW transceiver using a first channel of a plurality of channels; a second core MMW transceiver operable to convey a processing message with a processing module via a first processing module MMW transceiver using a second channel of a plurality of channels; and a third core MMW transceiver operable to communicate with a peripheral access control module using a third channel of a plurality of channels; and a peripheral access control module, wherein the peripheral access control module includes; a first peripheral access MMW transceiver operable to convey a peripheral message with one of a plurality of peripheral components; and a second peripheral MMW transceiver that communicates with the third core MMW transceiver to couple the core access control module with the peripheral access control module. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification