Method and system for minimizing power consumption in a communication system

• US 8,238,285 B2
• Filed: 10/04/2011
• Issued: 08/07/2012
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza
• Primary Examiner(s): DESIR, PIERRE LOUIS
• Application Number:
  US13/252,402
• Publication Number:
  US 20120093050A1
• Time in Patent Office: 308 Days
• Field of Search: 370/321, 370/347, 455/450, 455/555, 375/216, 375/316
• US Class Current: 370/321
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/207 A hybrid coupler being used as power measuring circuit at the output of an amplifier circuit
• CPC Class Codes: H03F 2200/321 Use of a microprocessor in an amplifier circuit or its control circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier

Abstract

A method for regulating power in a front-end circuit, the method includes determining, along a first communication path, an envelope of a baseband signal; generating at least one voltage control signal based on the determined envelope of the baseband signal; and adjusting one or both of power and/or gain of the front-end circuit using the generated at least one voltage control signal. The baseband signal is communicated to the front-end circuit using a second communication path. Signal delay along the second communication path is matched with signal delay along the first communication path. The at least one voltage control signal comprises a supply voltage signal and a bias voltage signal. The power of the front-end circuit may be adjusted using the supply voltage signal. The gain of the front-end circuit may be adjusted using the bias voltage signal.

Claims

1. A method for regulating power in a front-end circuit, the method comprising:

determining, along a first communication path, an envelope of a baseband signal;

generating at least one voltage control signal based on said determined envelope of said baseband signal; and

adjusting one or both of power and/or gain of the front-end circuit using said generated at least one voltage control signal, wherein said baseband signal is communicated to the front-end circuit using a second communication path, and wherein signal delay along said second communication path is matched with signal delay along said first communication path.

2. The method according to claim 1, wherein said at least one voltage control signal comprises a supply voltage signal and a bias voltage signal.

3. The method according to claim 2, comprising adjusting said power of the front-end circuit using said supply voltage signal.

4. The method according to claim 2, comprising adjusting said gain of the front-end circuit using said bias voltage signal.

5. The method according to claim 1, wherein said signal delay along said second communication path is matched with said signal delay along said first communication path by delaying said baseband signal by a number of samples.

6. The method according to claim 5, comprising calculating said number of samples by minimizing an amount of intermodulation distortion at an output of the front-end circuit.

7. The method according to claim 2, comprising generating said supply voltage signal and said bias voltage signal via a switching regulator.

8. The method according to claim 1, wherein said front-end circuit is an amplifier circuit.

9. A system for regulating power in a front-end circuit, the system comprising:

one or more circuits operable to determine, along a first communication path, an envelope of a baseband signal;

said one or more circuits are operable to generate at least one voltage control signal based on said determined envelope of said baseband signal; and

said one or more circuits are operable to adjust one or both of power and/or gain of the front-end circuit using said generated at least one voltage control signal, wherein said baseband signal is communicated to the front-end circuit using a second communication path, and wherein signal delay along said second communication path is matched with signal delay along said first communication path.

10. The system according to claim 9, wherein said at least one voltage control signal comprises a supply voltage signal and a bias voltage signal.

11. The system according to claim 10, wherein said one or more circuits are operable to adjust said power of the front-end circuit using said supply voltage signal.

12. The system according to claim 10, wherein said one or more circuits are operable to adjust said gain of the front-end circuit using said bias voltage signal.

13. The system according to claim 9, wherein said signal delay along said second communication path is matched with said signal delay along said first communication path by delaying said baseband signal by a number of samples.

14. The system according to claim 13, wherein said one or more circuits are operable to calculate said number of samples by minimizing an amount of intermodulation distortion at an output of the front-end circuit.

15. The system according to claim 10, wherein said one or more circuits are operable to generate said supply voltage signal and said bias voltage signal via a switching regulator.

16. The system according to claim 9, wherein said front-end circuit is an amplifier circuit.

17. A non-transitory machine-readable storage having stored thereon, a computer program having at least one code section for regulating power in a front-end circuit, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

determining, along a first communication path, an envelope of a baseband signal;

generating at least one voltage control signal based on said determined envelope of said baseband signal; and

adjusting one or both of power and/or gain of the front-end circuit using said generated at least one voltage control signal, wherein said baseband signal is communicated to the front-end circuit using a second communication path, and wherein signal delay along said second communication path is matched with signal delay along said first communication path.

18. The non-transitory machine-readable storage according to claim 17, wherein said at least one voltage control signal comprises a supply voltage signal and a bias voltage signal.

19. The non-transitory machine-readable storage according to claim 18, wherein said at least one code section comprises code that enables adjusting said power of the front-end circuit using said supply voltage signal.

20. The non-transitory machine-readable storage according to claim 18, wherein said at least one code section comprises code that enables adjusting said gain of the front-end circuit using said bias voltage signal.

21. The non-transitory machine-readable storage according to claim 17, wherein said signal delay along said second communication path is matched with said signal delay along said first communication path by delaying said baseband signal by a number of samples.

22. The non-transitory machine-readable storage according to claim 21, wherein said at least one code section comprises code that enables calculating said number of samples by minimizing an amount of intermodulation distortion at an output of the front-end circuit.

23. The non-transitory machine-readable storage according to claim 18, wherein said at least one code section comprises code that enables generating said supply voltage signal and said bias voltage signal via a switching regulator.

24. The non-transitory machine-readable storage according to claim 17, wherein said front-end circuit is an amplifier circuit.