Programmed I/O ethernet adapter with early interrupts for accelerating data transfer

• US 8,239,580 B2
• Filed: 11/04/2010
• Issued: 08/07/2012
• Est. Priority Date: 07/02/1992
• Status: Expired due to Fees

• Current Assignee: U.S. Ethernet Innovations
• Original Assignee: U.S. Ethernet Innovations
• Inventors: Hausman, Richard, Sherer, Paul William, Rivers, James P., Zikmund, Cynthia, Connery, Glenn W., Strohl, Niles E., Reid, Richard S.
• Primary Examiner(s): STRANGE, AARON N
• Application Number:
  US12/939,604
• Publication Number:
  US 20110047302A1
• Time in Patent Office: 642 Days
• Field of Search: 709/250, 719/321, 719/327
• US Class Current: 709/250
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9078 using an external memory or storage device

Abstract

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Claims

1. An apparatus comprising:

a host computer comprising a system bus; and

a data communications adapter comprising;

Ethernet control circuitry;

a host interface coupled to said system bus and configured to exchange data with said host computer via said system bus;

a transceiver coupled to receive and transmit data over communications media;

data transmit control circuitry responsive to said Ethernet control circuitry and coupled to said transceiver, to a transmit data buffer, and to said host interface, for generating a packet transmit signal causing said transceiver to begin transmitting data from said transmit data buffer over said communications media;

a receive data buffer coupled to said host interface; and

data receive control circuitry responsive to said Ethernet control circuitry and coupled to said transceiver, to said receive data buffer, and to said host interface, for storing data received by said transceiver in said receive data buffer, and for generating a receive interrupt signaling to said host computer that data has been received by said transceiver, wherein said data receive control circuitry is operative to generate said receive interrupt once said transceiver has received over said communications media a predetermined number of bytes of a data packet that is less than all of said data packet, wherein said Ethernet control circuitry, said host interface, said data receive control circuitry, said data transmit control circuitry, said receive data buffer, and said transmit data buffer are all contained in a single Application Specific Integrated Circuit (ASIC).

2. The apparatus of claim 1, wherein said data receive control circuitry is programmable.

3. The apparatus of claim 1, wherein said data transmit control circuitry is programmable to generate said packet transmit signal when said transmit data buffer contains the predetermined number of bytes of the data packet that is less than all of said data packet.

4. The apparatus of claim 1 wherein the receive data buffer is a ring buffer connected to the host interface via a DMA channel.

5. The apparatus of claim 1 wherein said host interface is coupled to said host computer.

6. A method performed on a host computer of transferring a packet of data from a computer network communications media through an adapter to a system bus coupled to a central processing unit (CPU) of the host computer, said method comprising the steps of:

receiving from said computer network communications media through a transceiver and storing in an adapter receive buffer a predetermined first receive threshold number of bytes of said packet of data;

generating a first early receive interrupt from said adapter to said CPU via the system bus;

adjusting said first receive threshold number of bytes according to a length of said packet of data;

continuing to receive from said computer network communications media through said transceiver and store in the adapter receive buffer bytes of said packet of data;

thereafter generating a second early receive interrupt from said adapter to said CPU via the system bus, prior to complete reception of said packet of data; and

storing from said communications media through said transceiver and storing in said adapter receive buffer a remainder of said packet of data;

wherein said host computer employs a driver allowing for early indications and having an early lookahead size associated with the predetermined first receive threshold number of bytes.

7. The method of claim 6, further comprising, after the step of generating said first early receive interrupt, the steps of:

a) evaluating the number of bytes stored in said adapter receive buffer against said early lookahead size; and

b) adjusting said first receive threshold number of bytes if said evaluating step does not indicate substantial equality.