System and method for an asynchronous data buffer having buffer write and read pointers

• US 8,239,607 B2
• Filed: 09/03/2009
• Issued: 08/07/2012
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US12/553,856
• Publication Number:
  US 20090319745A1
• Time in Patent Office: 1,069 Days
• Field of Search: 711/5, 711/167, 365/233.1
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Claims

1. A method, comprising:

storing read data in sequentially selected data locations of a buffer responsive to a first clock signal by providing a selection signal for sequentially selecting the data locations by shifting a first flag bit responsive to a rising edge of a strobe signal through a first set of series-coupled flip-flops having a last flip-flop coupled to a first flip-flop of the first set, and by shifting a second flag bit responsive to a falling edge of the strobe signal through a second set of series-coupled flip-flops having a last flip-flop coupled to a first flip-flop of the second set;

retrieving read data from sequentially selected data locations of the buffer responsive to a second clock signal;

determining a timing offset associated with coupling data between the first time domain and the second time domain; and

adjusting timing parameters responsive to the timing offset.

2. A method, comprising:

determining a timing offset between storing read data in sequentially selected data locations of a buffer responsive to a first clock signal and retrieving read data from sequentially selected data locations of the buffer responsive to a second clock signal, the data stored in the buffer by providing a selection signal for sequentially selecting the data locations by shifting a first flag bit in response to a rising edge of a strobe signal through a first set of series-coupled flip-flops having a last flip-flop coupled to a first flip-flop of the first set, and by shifting a second flag bit in response to a falling edge of the strobe signal through a second set of series-coupled flip-flops having a last flip-flop coupled to a first flip-flop of the second set; and

executing data transfer operations responsive to the timing offset.

3. An apparatus, comprising:

a synchronization module operable to couple data between a first time domain and a second time domain, the synchronization module comprising;

a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to a first clock signal, the first pointer circuit having a first set of series-coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series-coupled flip-flops operable to shift a first flag through each flip-flop in response to a rising edge of the first clock signal, and further having a second set of series-coupled flip-flops having an output of a last flip-flop coupled to an input of a second flip-flop, the second set of series-coupled flip-flops operable to shift a second flag through each flip-flop in response to a rising edge of the second clock signal, output signals of the flip-flops of the first and second sets of series-coupled flip-flops representative of the first pointer signal;

a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to a second clock signal; and

a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate a pointer offset signal indicative of a pointer offset.

4. A memory hub, comprising:

a link interface;

a memory device interface;

a memory controller coupled to the link interface and the memory device interface;

a synchronization module coupled to a memory device, the memory device interface and the memory controller, the memory device operating according to a first clock signal, the synchronization module operable to couple read data from the memory device to the memory controller, the memory controller operable to receive memory requests from the link interface responsive to a second clock signal, the synchronization module comprising;

a first pointer circuit, the first pointer circuit operable to generate a first pointer signal indicative of a data location in a buffer where data is to be stored in responsive to the first clock signal;

a second pointer circuit, the second pointer circuit operable to generate a second pointer signal indicative of a data location in the buffer where data is to be retrieved from responsive to the second clock signal; and

a comparison circuit coupled to the first pointer circuit and the second pointer circuit, the comparison circuit operable to compare the first pointer signal and the second pointer signal to generate a pointer offset signal indicative of a pointer offset;

a buffer coupled to the first pointer circuit, the buffer having a plurality of data locations;

a selection circuit coupled to the buffer and the second pointer circuit, the selection circuit operable to selectively couple data stored in the plurality of data locations of the buffer to an output terminal of the selection circuit responsive to the second clock signal; and

a data latch coupled to the output terminal of the selection circuit to latch the data selectively coupled thereto responsive to the first clock signal.

5. An apparatus, comprising:

a synchronization module operable to couple data between a first time domain and a second time domain, the synchronization module comprising;

a data buffer configured to be coupled to a memory device and having a plurality of data locations at which read data are respectively stored;

a write pointer circuit coupled to the data buffer and adapted to generate a write pointer signal to sequentially select one of the plurality of data locations of the data buffer for storing read data received from the memory device responsive to a strobe signal provided by the memory device;

a read pointer circuit coupled to the data buffer and adapted to generate responsive to the core clock signal a read pointer signal to sequentially select one of the plurality of data locations of the buffer from which the read data stored therein, the read pointer including a plurality of flip-flops adapted to output a respective bit of a count value responsive to the core clock signal; and

a write-read pointer compare circuit coupled to the write and read pointer circuits to compare the write and read pointer signals and adapted to generate a write-read pointer offset signal indicative of the comparison.

6. The apparatus of claim 5, further comprising a multiplexer coupled to the data buffer and the read pointer circuit, and configured to selectively couple read data stored at respective data locations of the data buffer to an output terminal in accordance with the read pointer signal.

7. The apparatus of claim 6, further comprising a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal.

8. The apparatus of claim 5 wherein the write pointer circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the strobe signal,

the write pointer signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

9. The apparatus of claim 8 wherein the write-read compare circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the read pointer signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

10. The apparatus of claim 9 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

11. The apparatus of claim 9, further comprising:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.

12. A data synchronizing circuit for coupling data between a memory controller clocked in accordance with a core clock signal and a memory device clocked in accordance with a memory device clock signal, the data synchronizing circuit comprising:

a data buffer having a plurality of memory locations at which to store data and a selection signal node, the data buffer coupled to the memory device to store read data at a respective one of the plurality of data locations selected in accordance with a selection signal;

a write pointer circuit coupled to the memory device to receive a data strobe signal and further coupled to the selection signal node of the data buffer to provide a selection signal to sequentially select a data location to which read data from the memory device is written in response to the data strobe signal;

a multiplexer having a plurality of input terminals coupled to a respective one of the plurality of data locations of the data buffer and further having an output terminal to which the input terminals are selectively coupled to couple read data from the data buffer to the output terminal according to a multiplexer selection signal applied to a multiplexer selection node;

a read pointer circuit having a clock node to which the core clock signal is applied and further having an output node coupled to the multiplexer selection node to provide the multiplexer selection signal to sequentially select the input terminals for coupling to the output terminal of the multiplexer responsive to the core clock signal;

a data latch coupled to the output terminal of the multiplexer to latch the read data selectively coupled thereto responsive to the core clock signal; and

a pointer comparison circuit coupled to the write and read pointer circuits to compare to which one of the data locations read data received from the memory device are currently stored and from which one of the data locations read data are currently coupled to the output terminal of the multiplexer and generate a write-read pointer offset signal indicative of the comparison.

13. The data synchronizing circuit of claim 12 wherein the read pointer circuit comprises a plurality of flip-flops adapted to output a respective bit of a count value in response to the core clock signal.

14. The data synchronizing circuit of claim 13 wherein the write pointer circuit comprises:

a first set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the first set of series coupled flip-flops shifting a flag through each flip-flop in response to a rising edge of the data strobe signal; and

a second set of series coupled flip-flops having an output of a last flip-flop coupled to an input of a first flip-flop, the second set of series coupled flip-flops shifting a flag through each flip-flop in response to a falling edge of the data strobe signal, the selection signal represented by output signals of the flip-flops of the first and second sets of series coupled flip-flops.

15. The data synchronizing circuit of claim 14 wherein the pointer comparison circuit comprises:

a logic circuit having a plurality of input nodes coupled to outputs of each flip-flop of the first and second sets of series coupled flip-flops and further having a plurality of output nodes, the logic circuit adapted to generate flag signals at each of the output nodes indicative of the location of the flag in the first and second sets of series coupled flip-flops;

a first multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the first multiplexer selectively coupling one of the input terminals to the output terminal according to the multiplexer selection signal provided by the read pointer circuit; and

a second multiplexer having a plurality of input terminals coupled to the plurality of output nodes of the logic circuit, a selection terminal coupled to the read pointer circuit, and further having an output terminal, the second multiplexer selectively coupling one of the input terminals to the output terminal according to the multiplexer selection signal provided by the read pointer circuit,

the outputs of the first and second multiplexers providing signals representative the write-read pointer offset signal.

16. The data synchronizing circuit of claim 15 wherein the logic circuit comprises a plurality of three-input logic OR gates, each logic OR gate having first and second inputs coupled to outputs of two flip-flops of the first set of series coupled flip-flops and further having a third input coupled to an output of a respective flip-flop of the second set of series coupled flip-flops.

17. The data synchronizing circuit of claim 15, further comprising:

a first pair of series coupled flip-flops coupled to the output terminal of the first multiplexer, the first pair of series coupled flip-flops shifting the output of the first multiplexer though the flip-flops in response to the core clock signal; and

a second pair of series coupled flip-flops coupled to the output terminal of the second multiplexer, the second pair of series coupled flip-flops shifting the output of the second multiplexer though the flip-flops in response to the core clock signal.