Error correction for a data storage device

• US 8,239,724 B2
• Filed: 08/07/2009
• Issued: 08/07/2012
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Swing, Andrew T., Borchers, Albert T., Sprinkle, Robert S., Klaus, Jason W., Norrie, Thomas J., Gelb, Benjamin S.
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US12/537,725
• Publication Number:
  US 20100262894A1
• Time in Patent Office: 1,096 Days
• Field of Search: None
• US Class Current: 714/752
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An apparatus for error correction for a data storage device may include an input interface that is configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, where each of the channel controllers is arranged and configured to control operations associated with one or more memory chips. The apparatus may include a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction using an error correction algorithm and the error correction information to generate correction solutions, where the corrector module is a shared resource for the multiple channel controllers. The apparatus may include an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers.

Claims

1. An apparatus for error correction for a data storage device, comprising:

an input interface that is arranged and configured to receive individual error correction requests to correct data from multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests, wherein each of the channel controllers is arranged and configured to control operations associated with one or more memory chips, wherein the input interface comprises;

a buffer that is arranged and configured to store the error correction requests from the channel controllers, and

combiner logic circuitry that is arranged in a tree structure and that is configured to serialize the individual error correction requests into a single request stream;

a corrector module that is operably coupled to the input interface and that is arranged and configured to perform error correction on the single request stream using an error correction algorithm and the error correction information to generate correction solutions, wherein the corrector module is a shared resource for the multiple channel controllers; and

an output interface that is operably coupled to the corrector module and that is arranged and configured to communicate the correction solutions to the channel controllers, wherein the output interface comprises expander logic circuitry that is configured to de-serialize the correction solutions and to broadcast the correction solutions to the channel controllers.

2. The apparatus of claim 1 wherein the input interface is arranged and configured to arbitrate an order that the corrector module performs the error correction responsive to the individual error correction requests from the channel controllers.

3. The apparatus of claim 2 wherein the input interface is arranged and configured to arbitrate the order using a round robin scheme.

4. The apparatus of claim 2 wherein the input interface is arranged and configured to arbitrate the order using a first-in first-out (FIFO) scheme.

5. The apparatus of claim 2 wherein the input interface is arranged and configured to arbitrate the order using a fixed priority scheme.

6. The apparatus of claim 1 wherein the error correction algorithm includes a Bose Chauduri Hocquenghem (BCH) error correction algorithm.

7. The apparatus of claim 1 wherein the output interface comprises expander logic circuitry that is arranged and configured to broadcast the correction solutions to the channel controllers.

8. The apparatus of claim 1 wherein the memory chips comprise flash memory chips.

9. The apparatus of claim 1 wherein the input interface, the corrector module, and the output interface are a part of a field programmable gate array (FPGA) controller.

10. A method for error correction for a data storage device, the method comprising:

receiving individual error correction requests to correct data from multiple channel controllers and receiving error correction information corresponding to the error correction requests, wherein each of the channel controllers is arranged and configured to control operations associated with one or more memory chips;

storing the error correction requests from the channel controllers in a buffer;

serializing the individual error correction requests into a single request stream;

performing error correction on the single request stream using an error correction algorithm and the error correction information to generate correction solutions;

de-serializing the correction solutions; and

communicating the correction solutions to the channel controllers.

11. The method as in claim 10 further comprising arbitrating an order for performing the error correction using a round robin scheme.

12. The method as in claim 10 further comprising arbitrating an order for performing the error correction using a first-in first-out (FIFO) scheme.

13. The method as in claim 10 further comprising arbitrating an order for performing the error correction using a fixed priority scheme.

14. The method as in claim 10 wherein performing error correction comprises performing error correction using a Bose Chauduri Hocquenghem (BCH) error correction algorithm.

15. The method as in claim 10 wherein communicating the correction solutions comprises broadcasting the correction solutions to the channel controllers.

16. A system for error detection and correction in a data storage device, comprising:

multiple channel controllers, wherein each of the channel controllers is arranged and configured to control operations associated with one or more memory chips and each of the channel controllers comprises an error encoder module that is arranged and configured to calculate error correction codes and an error detector module that is arranged and configured to detect errors in data read from the memory chips;

combiner logic circuitry that is operably coupled to the channel controllers and that is arranged in a tree structure and that is configured to serialize the individual error correction requests into a single request stream;

a corrector module that is operably coupled to the combiner logic circuitry and that is arranged and configured to perform error correction on the single request stream using an error correction algorithm to generate correction solutions responsive to the errors detected by the error detection modules in the channel controllers, wherein the correction module is a shared resource for the multiple channel controllers; and

expander logic circuitry that is operably coupled to the corrector module and that is arranged and configured to de-serialize the correction solutions and to broadcast the correction solutions to the channel controllers.

17. The system of claim 16 wherein each of the multiple channel controllers further comprises a channel corrector module that is arranged and configured to receive the correction solution from the expander logic circuitry and to apply the correction solutions to the data.

18. The system of claim 16 wherein the memory chips comprise flash memory chips.

19. The system of claim 16 further comprising an input interface that is operably coupled to the corrector module and to the channel controllers and that is arranged and configured to receive individual error correction requests to correct data from the multiple channel controllers and that is configured to receive error correction information corresponding to the error correction requests.

20. The system of claim 19 wherein the input interface comprises:

a buffer that is arranged and configured to store the error correction request from the channel controllers; and

the combiner logic circuitry.

21. The system of claim 16 further comprising an output interface that is operably coupled to the corrector module and to the channel controllers and that is arranged and configured to communicate the correction solutions to the channel controllers.

22. The system of claim 21 wherein the output interface comprises the expander logic circuitry.

23. The system of claim 16 wherein the channel controllers and the corrector module are a part of a field programmable gate array (FPGA) controller.

24. A data storage device, comprising:

multiple flash memory chips; and

a controller that is operably coupled to the flash memory chips and that is arranged and configured to receive commands from a host, wherein the controller comprises;

combiner logic circuitry that is arranged in a tree structure and that is configured to serialize the individual error correction requests into a single request stream;

a corrector module that is arranged and configured to perform error correction on the single request stream using an error correction algorithm to generate correction solutions responsive to errors in data being written to or read from the flash memory chips, wherein the correction module is a shared resource for the flash memory chips; and

expander logic circuitry that is arranged and configured to de-serialize the correction solutions and to broadcast the correction solutions.

25. The data storage device of claim 24 wherein the controller is a field programmable gate array (FPGA) controller.

26. The data storage device of claim 24 further comprising:

multiple channel controllers, wherein each of the channel controllers is arranged and configured to control operations associated with one or more of the flash memory chips and each of the channel controllers comprises an error encoder module that is arranged and configured to calculate error correction codes and an error detector module that is arranged and configured to detect the errors in data written to or read from the flash memory chips and to send error correction requests to the corrector module.

27. The data storage device of claim 26 wherein each of the channel controllers further comprises a channel corrector module that is arranged and configured to receive the correction solution from the expander logic circuitry and to apply the correction solutions to the data.

28. The data storage device of claim 24 further comprising:

a memory board on which the flash memory chips are arranged and configured into multiple channels, with each of the channels being associated with one or more of the flash memory chips; and

a controller board that is operably connected to the memory board, wherein the controller board comprises;

an interface; and

the controller that is arranged and configured to receive the commands from the host using the interface.

29. The data storage device of claim 28 wherein:

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

30. The data storage device of claim 24 further comprising:

two memory boards on which the flash memory chips are arranged and configured into multiple channels, with each of the channels being associated with one or more of the flash memory chips; and

a controller board that is operably connected to the memory boards, wherein the controller board comprises;

an interface; and

the controller that is arranged and configured to receive the commands from the host using the interface, wherein the memory boards are each separately removable from the controller board.