Error correction coding in flash memory devices
First Claim
1. A system that facilitates error correction of data in a non-volatile memory, comprising:
- an error correction code (ECC) component that generates at least one parity bit comprising a value based on a first set of data being written to a portion of the non-volatile memory, wherein the portion of the non-volatile memory comprises a second set of data stored thereon that is in addition to the first set of data;
an evaluation component that analyzes at least one of the second set of data, a stored parity code associated with the second set of data, and a stored indicator data associated with the second set of data, wherein the stored parity code and the stored indicator data are located in the portion of the non-volatile memory;
an indicator component that sets an indicator data associated with the first set of data as a function of the at least one parity bit and the analysis performed by the evaluation component; and
a controller component that, when the first set of data is being read from the non-volatile memory, facilitates enabling or disabling error correction of the first set of data based on the indicator data and communicates, to other system components, information related to an error detection and correction status of the first set of data;
wherein the non-volatile memory includes a plurality of memory locations, wherein at least one of data, a parity code, or indicator data, or a combination thereof, is written to, read from, or stored in, at least one memory location of the plurality of the memory locations.
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Accused Products
Abstract
Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to ‘1’ state) and can be disabled by programming the indicator bit (e.g., bit set to a ‘0’ state).
21 Citations
20 Claims
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1. A system that facilitates error correction of data in a non-volatile memory, comprising:
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an error correction code (ECC) component that generates at least one parity bit comprising a value based on a first set of data being written to a portion of the non-volatile memory, wherein the portion of the non-volatile memory comprises a second set of data stored thereon that is in addition to the first set of data; an evaluation component that analyzes at least one of the second set of data, a stored parity code associated with the second set of data, and a stored indicator data associated with the second set of data, wherein the stored parity code and the stored indicator data are located in the portion of the non-volatile memory; an indicator component that sets an indicator data associated with the first set of data as a function of the at least one parity bit and the analysis performed by the evaluation component; and a controller component that, when the first set of data is being read from the non-volatile memory, facilitates enabling or disabling error correction of the first set of data based on the indicator data and communicates, to other system components, information related to an error detection and correction status of the first set of data; wherein the non-volatile memory includes a plurality of memory locations, wherein at least one of data, a parity code, or indicator data, or a combination thereof, is written to, read from, or stored in, at least one memory location of the plurality of the memory locations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method that facilitates error correction of data, comprising:
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generating at least one parity bit based on data being programmed into a non-volatile memory location, wherein the non-volatile memory location comprises stored data that is in addition to the data being programmed; executing an operation in a non-volatile memory associated with the data being programmed or the stored data, the operation is at least one of a read, a program, a write buffer program, a word/byte program, or an erase; and at least one of enabling error correction or disabling error correction of the data being programmed or the stored data based on a value of a first indicator data associated with the data being programmed, at least one parity bit associated with the data being programmed, a second indicator data associated with the stored data, or a parity bit associated with the stored data. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A system that facilitates error correction of data, comprising:
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means for executing an operation related to data in a non-volatile memory, wherein the data comprises stored data and additional data programmed to the non-volatile memory; and means for at least one of enabling error correction or disabling error correction of the data based on; a value of a first indicator bit associated with the stored data and a value of a second indicator bit associated with the additional data programmed to the non-volatile memory; and a value of a first parity bit associated with the stored data and a second parity bit associated with the additional data programmed to the non-volatile memory. - View Dependent Claims (20)
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Specification