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Layout method and layout apparatus for semiconductor integrated circuit

  • US 8,239,803 B2
  • Filed: 07/27/2011
  • Issued: 08/07/2012
  • Est. Priority Date: 09/07/2007
  • Status: Expired due to Fees
First Claim
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1. A layout method of a semiconductor integrated circuit by using cell library data, said method comprising:

  • specifying a gate in a predetermined cell as a reference gate; and

    automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from said reference gate meets a preset gate data density condition.

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