Layout method and layout apparatus for semiconductor integrated circuit

• US 8,239,803 B2
• Filed: 07/27/2011
• Issued: 08/07/2012
• Est. Priority Date: 09/07/2007
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kobayashi, Naohiro
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/137,201
• Publication Number:
  US 20110289467A1
• Time in Patent Office: 377 Days
• Field of Search: 716/55, 716/118, 716/119, 716/122, 716/139, 438/403
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition.

Claims

1. A layout method of a semiconductor integrated circuit by using cell library data, said method comprising:

specifying a gate in a predetermined cell as a reference gate; and

automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from said reference gate meets a preset gate data density condition.

2. The layout method according claim 1, further comprising:

acquiring a layout coordinate of said gate in the predetermined cell,

wherein said automatically arranging the plurality of cells comprises;

referring to the layout coordinate of said gate to determine said area; and

automatically arranging said plurality of cells such that the number of gates arranged in said area meets said gate data density condition.

3. The layout method according to claim 2, wherein said cell library data comprises the layout coordinate of said gate, and

wherein said acquiring comprises:

extracting the layout coordinate of said gate from said cell library data.

4. The layout method according to claim 2, wherein said acquiring comprises:

calculating the layout coordinate of said gate by using layout coordinates of diffusion layers and a layout coordinate of a polysilicon layer.

5. The layout method according to claim 4, wherein said cell library data comprises the layout coordinates of the diffusion layers and the layout coordinate of the polysilicon layer, and

wherein said acquiring comprises:

extracting the layout coordinates of the diffusion layers and the layout coordinate of the polysilicon layer from said cell library data.

6. The layout method according to claim 1, wherein said specifying comprises:

selecting a gate arranged in a neighborhood to a cell frame in said predetermined cell as said reference gate.

7. The layout method according to claim 1, wherein said specifying the gate in the predetermined cell comprises:

selecting a gate arranged in a corner of said predetermined cell as said reference gate.