Highly integrated single chip set-top box

• US 8,239,914 B2
• Filed: 07/22/2005
• Issued: 08/07/2012
• Est. Priority Date: 07/22/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kuhlmann, Martin, Gomez, Ramon A., Tan, Loke
• Primary Examiner(s): Tran, Hai V
• Assistant Examiner(s): Mendoza, Junior
• Application Number:
  US11/187,009
• Publication Number:
  US 20060026657A1
• Time in Patent Office: 2,573 Days
• Field of Search: 725/151
• US Class Current: 725/151
• CPC Class Codes: H04N 21/41 Structure of client; Structure of client peripherals
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4383 Accessing a communication channel

Abstract

A highly integrated set-top box is implemented on a single semiconductor substrate. For instance, an analog RF tuner is implemented on the same substrate with a digital receiver, and audio-video back-end circuits. The single chip set-top box can be used for satellite, cable, internet, or terrestrial TV applications, or other applications. As a result, the substrate area, assembly time, and associated costs per chip are reduced.

Claims

1. A set-top box, comprising:

a common single chip semiconductor substrate;

an analog tuner;

a digital receiver coupled to an output of said analog tuner; and

one or more audio and video back-end circuits coupled to an output of said digital receiver, said analog tuner, said digital receiver, and said one or more audio and video back-end circuits being implemented on said common single chip semiconductor substrate, wherein

said analog tuner includes;

a quadrature down-conversion circuit configured to produce a quadrature down-converted signal by mixing a radio frequency (RF) signal received at an input of said analog tuner with a quadrature local oscillator signal;

a direct digital frequency synthesizer (DDFS) configured to produce a digital representation of said quadrature local oscillator signal including independently generated quadrature components determined from a stored lookup table;

at least one digital-to-analog-converter (DAC), coupled to said DDFS, configured to sample said digital representation of said quadrature local oscillator signal to provide an analog local oscillator signal; and

at least one phase locked loop circuit (PLL), coupled to said at least one DAC, configured to multiply said analog local oscillator signal with a fixed value to provide said quadrature local oscillator signal, said fixed value being associated with a sampling frequency of said DAC.

2. The set-top box of claim 1, wherein said analog tuner is a single conversion tuner that is configured to down-convert a selected channel from a plurality of channels received at an RF input of said single conversion tuner.

3. The set-top box of claim 2, wherein said digital receiver is a QPSK digital receiver.

4. The set-top box of claim 1, wherein said one or more audio and video backend circuits comprises:

a divider module, coupled to said output of said digital receiver, configured to separate a video portion from an audio portion of said output of said digital receiver;

a video module, coupled to said divider module output, configured to process said video portion of said output of said digital receiver; and

an audio module, coupled to said divider module output, configured to process said audio portion of said output of said digital receiver.

5. The set-top box of claim 4, further comprising:

a universal serial bus interface, disposed on said common single chip semiconductor substrate, coupled to said audio and video modules.

6. The set-top box of claim 1, further comprising:

an AV security device disposed on said common single chip semiconductor substrate.

7. The set-top box of claim 1, further comprising:

an external memory interface disposed on said common single chip semiconductor substrate.

8. The set-top box of claim 7, wherein said external memory interface is a dynamic random access memory (DRAM) interface.

9. The set-top box of claim 1, further comprising:

a peripheral interface disposed on said common single chip semiconductor substrate.

10. The set-top box of claim 1, wherein said analog tuner is a direct conversion analog tuner.

11. The set-top box of claim 1, wherein an output of said digital receiver includes Moving Picture Experts Group (MPEG) packets, and wherein said one or more audio and video back-end circuits comprises:

a divider module configured to separate video MPEG packets from audio MPEG packets.

12. The set-top box of claim 11, wherein said one or more audio and video back-end circuits comprises:

a video module configured to process said video MPEG packets to produce a video output; and

an audio module configured to process said audio MPEG packets to produce an audio output.

13. The set-top box of claim 12, wherein said video module comprises:

a video decoder configured to decode said video MPEG packets;

a graphics module, coupled to an output of said video decoder, configured to add text to said video MPEG packets;

a video encoder, coupled to an output of said graphics module; and

a video digital-to-analog converter configured to convert an output of said video encoder to analog.

14. The set-top box of claim 12, wherein said audio module comprises:

an MPEG audio decoder configured to receive and to decode said audio MPEG packets; and

an audio digital-to-analog converter, coupled to an output of said MPEG audio decoder, configured to convert an output of said MPEG audio decoder to analog.

15. The set-top box of claim 1, further comprising:

an in-phase/quadrature-phase (IQ) error detection circuit configured to determine an IQ error of said quadrature down-converted signal.

16. The set-top box of claim 15, further comprising:

a local oscillator circuit configured to generate said quadrature local oscillator signal based on an output of said IQ error detection circuit.

17. The set-top box of claim 16, wherein said local oscillator circuit is configured to correct any IQ phase imbalance determined by said IQ error detection circuit.

18. The set-top box of claim 17, wherein said local oscillator circuit comprises:

at least one low pass filter (LPF) coupled to said at least one DAC.

19. The set-top box of claim 1, wherein said lookup table further comprises:

at least one of a phase value, a sine value, and a cosine value for generating said quadrature local oscillator signal.

20. The set-top box of claim 1, wherein said DDFS is configured to adjust at least one of a frequency, a gain, and a phase of said quadrature local oscillator signal, using at least one of a frequency offset value of said stored lookup table and said phase offset value, to reduce at least one of a frequency, a gain, and a phase mismatch of at least one of said quadrature components of said quadrature local oscillator signal.

21. The set-top box of claim 1, wherein said analog tuner comprises:

an analog-to-digital converter (ADC), coupled to an output of said quadrature down-conversion circuit, configured to digitize said quadrature down-converted signal; and

a demodulation circuit, coupled to an output of said ADC, configured to demodulate said digitized quadrature down-converted signal to produce a data output.

22. The set-top box of claim 21, further comprising:

a de-multiplexer coupled between said output of said ADC and an input of said demodulation circuit.

23. The set-top box of claim 21, further comprising:

an equalizer coupled between said ADC converter and said demodulation circuit, said equalizer configured to perform IQ imbalance correction.

24. The set-top box of claim 23, wherein said equalizer comprises:

a non-decision directed portion configured to receive an output of said ADC converter and a decision directed portion coupled to an output of said non-decision directed portion.

25. The set-top box of claim 23, wherein said equalizer comprises:

a non-decision directed portion configured to receive an output of said ADC converter.

26. The set-top box of claim 23, wherein said equalizer comprises:

a decision directed portion configured to receive an output of said ADC converter.

27. The set-top box of claim 21, further comprising:

a multiplexer coupled between said output of said quadrature down-conversion circuit and an input of said ADC.

28. The set-top box of claim 27, wherein said multiplexer is configured to interleave a first down-converted quadrature component and a second down-converted quadrature component of said quadrature down-converted signal to provide an interleaved sampling of said quadrature down-converted signal to said ADC, and said ADC is configured to convert said interleaved sampling of said quadrature down-converted signal to a digital representation.

29. The set-top box of claim 1, wherein said stored lookup table further comprises:

a phase offset value for correcting a phase difference between said quadrature components; and

a frequency offset value for indicating a difference between a current operating frequency of a local oscillator and a desired operating frequency of said local oscillator,

wherein said current operating frequency is calculated by multiplying a clock signal with a frequency control word associated with said local oscillator, said frequency control word being calculated based on said frequency offset value.

30. The set-top box of claim 29, wherein said current operating frequency is combined with said frequency offset value to change said current operating frequency to be equal to said desired operating frequency.